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Fix latches in i3c_target_fsm
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Signed-off-by: Krzysztof Boronski <[email protected]>
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kboronski-ant committed Nov 14, 2024
1 parent 76b4fdb commit 2f3de09
Showing 1 changed file with 9 additions and 2 deletions.
11 changes: 9 additions & 2 deletions src/ctrl/i3c_target_fsm.sv
Original file line number Diff line number Diff line change
Expand Up @@ -177,6 +177,8 @@ module i3c_target_fsm
// by a later address read
logic tbit_after_byte_d;

logic tbit_after_byte_write;

// IBI
logic ibi_handling; // Asserted when an IBI is transmitter
logic ibi_payload; // Asserted when data from IBI queue is transmitter
Expand Down Expand Up @@ -274,7 +276,7 @@ module i3c_target_fsm
if (!rst_ni) begin
tbit_after_byte_q <= 1'b0;
end else begin
tbit_after_byte_q <= tbit_after_byte_d;
tbit_after_byte_q <= tbit_after_byte_write ? tbit_after_byte_d : tbit_after_byte_q;
end
end

Expand Down Expand Up @@ -525,7 +527,9 @@ module i3c_target_fsm
event_read_cmd_received_o = 1'b0;
ibi_fifo_rready_o = 1'b0;
tx_host_nack_o = 1'b0;
command_code_valid = 0;
// TODO: Move this somewhere else - these are not a state outputs
command_code_valid = 1'b0;
restart_det_d = 1'b0;

unique case (state_q)
// Idle: initial state, SDA is released (high), SCL is released if the
Expand Down Expand Up @@ -891,6 +895,8 @@ module i3c_target_fsm
bus_rstart_det_o = 1'b0;
sel_od_pp_o = 1'b0;
defining_byte_valid = 1'b0;
tbit_after_byte_d = 1'b0;
tbit_after_byte_write = 1'b0;
unique case (state_q)
// Idle: initial state, SDA and SCL are released (high)
Idle: begin
Expand Down Expand Up @@ -942,6 +948,7 @@ module i3c_target_fsm
// We assume here that dynamic address takes precedence over the
// static address since sections 5.1.2 and 5.1.2.1.1 hint at this
// interpretation but it's not explicitly written anywhere
tbit_after_byte_write = 1'b1;
if (is_dyn_addr_match) begin
state_d = AddrAckWait;
tbit_after_byte_d = 1'b1;
Expand Down

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