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lit framework demostration
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sequencer committed Jan 20, 2024
1 parent 60da186 commit 5c552b0
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16 changes: 16 additions & 0 deletions lit/tests/CompilerPlugin/WithCompilerPlugin.sc
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// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED --enable-preview -Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s

import chisel3._
import circt.stage.ChiselStage
class FooBundle extends Bundle {
val foo = Input(UInt(3.W))
}
// CHECK-LABEL: module FooModule
// CHECK: input clock : Clock
// CHECK: input reset : UInt<1>
class FooModule extends Module {
// CHECK: output io : { flip foo : UInt<3>}
val io = IO(new FooBundle)
// CHECK: skip
}
println(ChiselStage.emitCHIRRTL(new FooModule))
12 changes: 12 additions & 0 deletions lit/tests/CompilerPlugin/WithoutCompilerPlugin.sc
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// RUN: not scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --java-opt="--enable-native-access=ALL-UNNAMED --enable-preview -Djava.library.path=%JAVALIBRARYPATH" %s 2>&1 | FileCheck %s

import chisel3._
import circt.stage.ChiselStage
class FooBundle extends Bundle {
val foo = Input(UInt(3.W))
}
class FooModule extends Module {
// CHECK: assertion failed: The Chisel compiler plugin is now required for compiling Chisel code.
val io = IO(new FooBundle)
}
println(ChiselStage.emitCHIRRTL(new FooModule))
16 changes: 16 additions & 0 deletions lit/tests/lit.cfg.py
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import platform
import lit.formats
from lit.llvm import llvm_config
from lit.llvm.subst import ToolSubst

config.name = 'CHISEL'
config.test_format = lit.formats.ShTest(True)
config.suffixes = [".sc"]
config.substitutions = [
('%SCALAVERSION', config.scala_version),
('%RUNCLASSPATH', ':'.join(config.run_classpath)),
('%SCALAPLUGINJARS', ':'.join(config.scala_plugin_jars)),
('%JAVAHOME', config.java_home),
('%JAVALIBRARYPATH', ':'.join(config.java_library_path))
]
config.test_source_root = os.path.dirname(__file__)
9 changes: 9 additions & 0 deletions lit/tests/lit.site.cfg.py.in
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import sys
config.scala_version = "@SCALA_VERSION@"
config.run_classpath = "@RUN_CLASSPATH@".split(",")
config.scala_plugin_jars = "@SCALA_PLUGIN_JARS@".split(",")
config.java_home = "@JAVA_HOME@"
config.java_library_path = "@JAVA_LIBRARY_PATH@".split(",")
config.chisel_lit_dir = "@CHISEL_LIT_DIR@".split(",")
config.test_exec_root = os.path.dirname(__file__)
lit_config.load_config(config, "@CHISEL_LIT_DIR@/tests/lit.cfg.py")
23 changes: 23 additions & 0 deletions lit/utility/src/package.scala
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import chisel3._

package object utility {
object binding {
def streamString(module: => RawModule, stream: chisel3.internal.CIRCTConverter => geny.Writable): String = Seq(
new chisel3.stage.phases.Elaborate,
chisel3.internal.panama.Convert
).foldLeft(
firrtl.AnnotationSeq(Seq(chisel3.stage.ChiselGeneratorAnnotation(() => module)))
) { case (annos, phase) => phase.transform(annos) }
.collectFirst {
case chisel3.internal.panama.circt.PanamaCIRCTConverterAnnotation(converter) =>
val string = new java.io.ByteArrayOutputStream
stream(converter).writeBytesTo(string)
new String(string.toByteArray)
}
.get

def firrtlString(module: => RawModule): String = streamString(module, _.firrtlStream)

def verilogString(module: => RawModule): String = streamString(module, _.verilogStream)
}
}

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