Update src/test/scala/chiselTests/experimental/FlatIOSpec.scala

chipsalliance · May 30, 2024 · 430bcc2 · 430bcc2
1 parent 92ea454
commit 430bcc2
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
@@ -112,9 +112,7 @@ class FlatIOSpec extends ChiselFlatSpec with MatchesAndOmits {
       val io = FlatIO(Input(new MyRecord))
     }
     matchesAndOmits(
-      ChiselStage.emitSystemVerilog(
-        new MyModule
-      )
+      ChiselStage.emitSystemVerilog(new MyModule)
     )("io_bar,")("io_foo,")
     matchesAndOmits(
       ChiselStage.emitSystemVerilog(new MyFlatIOModule)