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Merge pull request #4583 from chipsalliance/dev/seldridge/move-to-Fil…
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…eCheck

Move tests to FileCheck. Delete `matchesAndOmits`.
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@seldridge
seldridge authored Dec 28, 2024
2 parents 841dc01 + 386e1b3 commit 08b3342
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Showing 17 changed files with 2,052 additions and 1,918 deletions.
224 changes: 117 additions & 107 deletions src/test/scala/chiselTests/BoringUtilsSpec.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ abstract class ShouldntAssertTester(cyclesToWait: BigInt = 4) extends BasicTeste
when(done) { stop() }
}

class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with MatchesAndOmits {
class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with FileCheck {
val args = Array("--throw-on-first-error", "--full-stacktrace")

class BoringInverter extends Module {
Expand Down Expand Up @@ -151,21 +151,22 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
b := BoringUtils.bore(bar.b_wire)
c := BoringUtils.bore(c_wire)
}
matchesAndOmits(circt.stage.ChiselStage.emitCHIRRTL(new Foo, args))(
"module Baz :",
"output a_bore : UInt<1>",
"connect a_bore, a_wire",
"module Bar :",
"output b_bore : UInt<2>",
"connect a_bore, baz.a_bore",
"connect b_bore, b_wire",
"module Foo :",
"connect a, a_bore",
"connect b, b_bore",
"connect c, c_wire",
"connect a_bore, bar.a_bore",
"connect b_bore, bar.b_bore"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Baz :
|CHECK: output a_bore : UInt<1>
|CHECK: connect a_bore, a_wire
|CHECK-LABEL: module Bar :
|CHECK: output b_bore : UInt<2>
|CHECK: connect a_bore, baz.a_bore
|CHECK: connect b_bore, b_wire
|CHECK-LABEL: module Foo :
|CHECK: connect a, a_bore
|CHECK: connect b, b_bore
|CHECK: connect c, c_wire
|CHECK: connect a_bore, bar.a_bore
|CHECK: connect b_bore, bar.b_bore
|""".stripMargin
)
}

it should "bore up and down through the lowest common ancestor" in {
Expand All @@ -182,18 +183,19 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
val baz = Module(new Baz(bar.a))
}

matchesAndOmits(circt.stage.ChiselStage.emitCHIRRTL(new Foo))(
"module Bar :",
"output b_bore : UInt<1>",
"connect b_bore, a",
"module Baz :",
"input b_bore : UInt<1>",
"wire b_bore_1 : UInt<1>",
"connect b_bore_1, b_bore",
"connect b, b_bore_1",
"module Foo",
"connect baz.b_bore, bar.b_bore"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: output b_bore : UInt<1>
|CHECK: connect b_bore, a
|CHECK-LABEL: module Baz :
|CHECK: input b_bore : UInt<1>
|CHECK: wire b_bore_1 : UInt<1>
|CHECK: connect b, b_bore_1
|CHECK: connect b_bore_1, b_bore
|CHECK-LABEL: module Foo
|CHECK: connect baz.b_bore, bar.b_bore
|""".stripMargin
)
}

it should "not create input probes" in {
Expand Down Expand Up @@ -255,12 +257,13 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
val bar = Instance(Definition((new Bar)))
val sink = BoringUtils.bore(bar.out)
}
matchesAndOmits(circt.stage.ChiselStage.emitCHIRRTL(new Foo, args))(
"module Bar :",
"output out : UInt<1>",
"module Foo :",
"connect sink, bar.out"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: output out : UInt<1>
|CHECK-LABEL: module Foo :
|CHECK: connect sink, bar.out
|""".stripMargin
)
}

it should "work if driving an Instance's input port" in {
Expand All @@ -273,12 +276,13 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
val bar = Instance(Definition((new Bar)))
val source = BoringUtils.drive(bar.in)
}
matchesAndOmits(circt.stage.ChiselStage.emitCHIRRTL(new Foo, args))(
"module Bar :",
"input in : UInt<1>",
"module Foo :",
"connect bar.in, source"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: input in : UInt<1>
|CHECK-LABEL: module Foo :
|CHECK: connect bar.in, source
|""".stripMargin
)
}

it should "work boring upwards" in {
Expand All @@ -291,15 +295,16 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
val a = IO(Input(UInt(1.W)))
val bar = Module(new Bar(a))
}
matchesAndOmits(circt.stage.ChiselStage.emitCHIRRTL(new Foo))(
"module Bar :",
"input q_bore : UInt<1>",
"connect q, q_bore_1", // Do normal connection before secret ones
"connect q_bore_1, q_bore",
"module Foo :",
"input a : UInt<1>",
"connect bar.q_bore, a"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: input q_bore : UInt<1>
|CHECK: connect q, q_bore_1
|CHECK: connect q_bore_1, q_bore
|CHECK-LABEL: module Foo :
|CHECK: input a : UInt<1>
|CHECK: connect bar.q_bore, a
|""".stripMargin
)
}

it should "be included in DataMirror.modulePorts" in {
Expand Down Expand Up @@ -389,10 +394,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
a := BoringUtils.bore(bar.baz.a)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)
matchesAndOmits(chirrtl)()(
"connect a_bore, a"
)
(circt.stage.ChiselStage.emitCHIRRTL(new Foo) should not).include("connect a_bore, a")
}

it should "bore from a Probe" in {
Expand All @@ -413,10 +415,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
a := read(BoringUtils.bore(bar.baz.a))
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)
matchesAndOmits(chirrtl)()(
"connect a_bore, a"
)
(circt.stage.ChiselStage.emitCHIRRTL(new Foo) should not).include("connect a_bore, a")
}

it should "bore from a Property" in {
Expand All @@ -436,13 +435,14 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
a := BoringUtils.bore(bar.baz.a)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)

matchesAndOmits(chirrtl)(
"output a_bore : Integer",
"propassign a_bore, baz.a",
"propassign a, bar.a_bore"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: output a_bore : Integer
|CHECK: propassign a_bore, baz.a
|CHECK-LABEL: public module Foo :
|CHECK: propassign a, bar.a_bore
|""".stripMargin
)
}

it should "bore from an opaque type that wraps a Property" in {
Expand All @@ -468,13 +468,15 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
a := BoringUtils.bore(bar.baz.a)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: output a_bore : Integer
|CHECK: propassign a_bore, baz.a
|CHECK-LABEL: public module Foo :
|CHECK: propassign a_bore, bar.a_bore
|""".stripMargin
)

matchesAndOmits(chirrtl)(
"output a_bore : Integer",
"propassign a_bore, baz.a",
"propassign a_bore, bar.a_bore"
)()
}

it should "bore from nested opaque types that wrap a Property" in {
Expand Down Expand Up @@ -506,13 +508,14 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
a := BoringUtils.bore(bar.baz.a)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)

matchesAndOmits(chirrtl)(
"output a_bore : Integer",
"propassign a_bore, baz.a",
"propassign a_bore, bar.a_bore"
)()
generateFirrtlAndFileCheck(new Foo)(
"""|CHECK-LABEL: module Bar :
|CHECK: output a_bore : Integer
|CHECK: propassign a_bore, baz.a
|CHECK-LABEL: public module Foo :
|CHECK: propassign a_bore, bar.a_bore
|""".stripMargin
)
}

behavior.of("BoringUtils.drive")
Expand Down Expand Up @@ -545,15 +548,17 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
BoringUtils.drive(foo.a) := 1.B
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Bar)
generateFirrtlAndFileCheck(new Bar)(
"""|CHECK-LABEL: module Foo :
|CHECK: input bore
|CHECK: connect a, bore
|CHECK-LABEL: module Bar :
|CHECK: wire bore
|CHECK: connect bore, UInt<1>(0h1)
|CHECK: connect foo.bore, bore
|""".stripMargin
)

matchesAndOmits(chirrtl)(
"input bore",
"connect a, bore",
"wire bore",
"connect bore, UInt<1>(0h1)",
"connect foo.bore, bore"
)()
}

it should "bore ports for driving properties" in {
Expand All @@ -567,13 +572,14 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
BoringUtils.drive(foo.a) := Property(1)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Bar)

matchesAndOmits(chirrtl)(
"input bore",
"propassign a, bore",
"propassign foo.bore, Integer(1)"
)()
generateFirrtlAndFileCheck(new Bar)(
"""|CHECK-LABEL: module Foo :
|CHECK: input bore :
|CHECK: propassign a, bore
|CHECK-LABEL: public module Bar :
|CHECK: propassign foo.bore, Integer(1)
|""".stripMargin
)
}

it should "bore to the final instance, but not into it, for inputs" in {
Expand All @@ -591,13 +597,14 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
BoringUtils.drive(bar.foo.a) := Property(1)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Baz)

matchesAndOmits(chirrtl)(
"input bore",
"propassign foo.a, bore",
"propassign bar.bore, Integer(1)"
)()
generateFirrtlAndFileCheck(new Baz)(
"""|CHECK-LABEL: module Bar :
|CHECK: input bore :
|CHECK: propassign foo.a, bore
|CHECK-LABEL: public module Baz :
|CHECK: propassign bar.bore, Integer(1)
|""".stripMargin
)
}

it should "bore into the final instance for outputs" in {
Expand All @@ -615,13 +622,16 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
BoringUtils.drive(bar.foo.a) := Property(1)
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Baz)

matchesAndOmits(chirrtl)(
"input bore",
"propassign a, bore",
"propassign foo.bore, bore",
"propassign bar.bore, Integer(1)"
)()
generateFirrtlAndFileCheck(new Baz)(
"""|CHECK-LABEL: module Foo :
|CHECK: input bore :
|CHECK: propassign a, bore
|CHECk-LABEL: module Bar :
|CHECK: input bore :
|CHECK: propassign foo.bore, bore
|CHECK-LABEL: public module Baz :
|CHECK: propassign bar.bore, Integer(1)
|""".stripMargin
)
}
}
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