[update] UDS Provisioning new flow #1860
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mhatrevi
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| 3. Following the DMA operation, the ROM updates the `UDS_PROGRAM_REQ` bit in the `CPTRA_DBG_MANUF_SERVICE_RSP_REG` register to either `UDS_PROGRAM_SUCCESS` or `UDS_PROGRAM_FAIL`, indicating the outcome of the operation. | ||
| 3. ROM then retrieves the SS_OTP_FC_UDS_GRANULARITY from `SS_DBG_MANUF_SERVICE_REG_REQ` register Bit3 to learn if the fuse row is accessible with 32-bit or 64-bit granularity. |
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| 3. ROM then retrieves the SS_OTP_FC_UDS_GRANULARITY from `SS_DBG_MANUF_SERVICE_REG_REQ` register Bit3 to learn if the fuse row is accessible with 32-bit or 64-bit granularity. | |
| 3. ROM then retrieves the `SS_OTP_FC_UDS_GRANULARITY` from `SS_DBG_MANUF_SERVICE_REG_REQ` register Bit3 to learn if the fuse row is accessible with 32-bit or 64-bit granularity. |
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| 4. The manufacturing process then polls this bit and continues with the fuse burning flow as outlined by the fuse controller specifications and SOC-specific VR methodologies. | ||
| 4. ROM then performs the following steps until all the 512-bits of the UDS seed are programmed: |
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| 4. ROM then performs the following steps until all the 512-bits of the UDS seed are programmed: | |
| 4. ROM then performs the following steps until all the 512 bits of the UDS seed are programmed: |
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| 7. ROM then resets the `UDS_PROGRAM_IN_PROGRESS` bit in the `SS_DBG_MANUF_SERVICE_REG_RSP` register to indicate completion of the programming. | ||
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| 8. The manufacturing process then polls this bit and continues with the fuse burning flow as outlined by the fuse controller specifications and SOC-specific VR methodologies. |
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The docs also suggest that locking is not complete until the next reset. Should we also explicitly require that the part is reset and the digest is verified?
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