User/anjpar/fuse ctrl changes

src/axi/rtl/axi_pkg.sv

@@ -14,6 +14,12 @@
 //
 
 package axi_pkg;
+    localparam int AXI_DW = 32;
+    localparam int AXI_AW = 32;
+    localparam int AXI_UW = 32;
+    localparam int AXI_IW = 1;
+    localparam int AXI_BC = AXI_DW/8;
+    localparam int AXI_BW = $clog2(AXI_BC);
 
     localparam AXI_LEN_MAX_VALUE = 256; // 8-bit LEN signal = 256 beats max
     localparam AXI_LEN_WIDTH     = $clog2(AXI_LEN_MAX_VALUE);

src/axi/rtl/axi_sub.sv

@@ -57,6 +57,7 @@ module axi_sub import axi_pkg::*; #(
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
     output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
+    output logic [2:0]    size,
     input  logic [DW-1:0] rdata, // Requires: Component dwidth == AXI dwidth
     output logic          last, // Asserted with final 'dv' of a burst
     input  logic          hld,
@@ -80,6 +81,7 @@ module axi_sub import axi_pkg::*; #(
     logic [AW-1:0] r_addr;  // Byte address
     logic [UW-1:0] r_user;
     logic [IW-1:0] r_id;
+    logic [2:0]    r_size;
     logic          r_last;  // Asserted with final 'dv' of a burst
     logic          r_hld;
     logic          r_err;
@@ -93,6 +95,7 @@ module axi_sub import axi_pkg::*; #(
     logic [IW-1:0] w_id;
     logic [DW-1:0] w_wdata; // Requires: Component dwidth == AXI dwidth
     logic [BC-1:0] w_wstrb; // Requires: Component dwidth == AXI dwidth
+    logic [2:0]    w_size; 
     logic          w_last;  // Asserted with final 'dv' of a burst
     logic          w_hld;
     logic          w_err;
@@ -125,6 +128,7 @@ module axi_sub import axi_pkg::*; #(
         .id   (w_id   ),
         .wdata(w_wdata),
         .wstrb(w_wstrb),
+        .wsize(w_size ),
         .last (w_last ),
         .hld  (w_hld  ),
         .err  (w_err  )
@@ -157,6 +161,7 @@ module axi_sub import axi_pkg::*; #(
         .addr (r_addr ),
         .user (r_user ),
         .id   (r_id   ),
+        .size (r_size ),
         .last (r_last ),
         .hld  (r_hld  ),
         .err  (r_err  ),
@@ -181,6 +186,7 @@ module axi_sub import axi_pkg::*; #(
         .r_user (r_user ),
         .r_id   (r_id   ),
         .r_last (r_last ),
+        .r_size (r_size ),
         .r_hld  (r_hld  ),
         .r_err  (r_err  ),
         .r_rdata(r_rdata),
@@ -192,6 +198,7 @@ module axi_sub import axi_pkg::*; #(
         .w_id   (w_id   ),
         .w_wdata(w_wdata),
         .w_wstrb(w_wstrb),
+        .w_size (w_size ),
         .w_last (w_last ),
         .w_hld  (w_hld  ),
         .w_err  (w_err  ),
@@ -204,6 +211,7 @@ module axi_sub import axi_pkg::*; #(
         .id     (id     ),
         .wdata  (wdata  ),
         .wstrb  (wstrb  ),
+        .size   (size   ),
         .last   (last   ),
         .hld    (hld    ),
         .rd_err (rd_err ),

src/axi/rtl/axi_sub_arb.sv

@@ -44,6 +44,7 @@ module axi_sub_arb import axi_pkg::*; #(
     input  logic [AW-1:0] r_addr,  // Byte address
     input  logic [UW-1:0] r_user,
     input  logic [IW-1:0] r_id,
+    input  logic [2:0]    r_size,
     input  logic          r_last,  // Asserted with final 'dv' of a burst
     output logic          r_hld,
     output logic          r_err,
@@ -57,6 +58,7 @@ module axi_sub_arb import axi_pkg::*; #(
     input  logic [IW-1:0] w_id,
     input  logic [DW-1:0] w_wdata, // Requires: Component dwidth == AXI dwidth
     input  logic [BC-1:0] w_wstrb, // Requires: Component dwidth == AXI dwidth
+    input  logic [2:0]    w_size,
     input  logic          w_last,  // Asserted with final 'dv' of a burst
     output logic          w_hld,
     output logic          w_err,
@@ -69,6 +71,7 @@ module axi_sub_arb import axi_pkg::*; #(
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
     output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
+    output logic [2:0]    size,
     output logic          last, // Asserted with final 'dv' of a burst
     input  logic          hld,
     input  logic          rd_err, // Asserts with rdata for reads (when C_LAT > 0)
@@ -125,6 +128,7 @@ module axi_sub_arb import axi_pkg::*; #(
         user    = r_win ? r_user : w_user;
         id      = r_win ? r_id   : w_id  ;
         last    = r_win ? r_last : w_last;
+        size    = r_win ? r_size : w_size;
         r_hld   = hld || !r_win;
         w_hld   = hld ||  r_win;
         r_err   = rd_err;

src/axi/rtl/axi_sub_rd.sv

@@ -61,6 +61,7 @@ module axi_sub_rd import axi_pkg::*; #(
     output logic [AW-1:0] addr, // Byte address
     output logic [UW-1:0] user,
     output logic [IW-1:0] id,
+    output logic [2:0]    size,
     output logic          last, // Asserted with final 'dv' of a burst
     input  logic          hld,
     input  logic          err,
@@ -192,9 +193,10 @@ module axi_sub_rd import axi_pkg::*; #(
     // Address Calculations                    //
     // --------------------------------------- //
     // Force aligned address to component
-    always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)};
+    always_comb addr = {txn_ctx.addr[AW-1:0]};//,BW'(0)};
     always_comb user = txn_ctx.user;
     always_comb id   = txn_ctx.id;
+    always_comb size = txn_ctx.size;
     always_comb last = txn_cnt == 0;
 
     // Use full address to calculate next address (in case of arsize < data width)

src/axi/rtl/axi_sub_wr.sv

@@ -59,6 +59,7 @@ module axi_sub_wr import axi_pkg::*; #(
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
     output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
+    output logic [2:0]    wsize,
     output logic          last, // Asserted with final 'dv' of a burst
     input  logic          hld,
     input  logic          err
@@ -233,7 +234,7 @@ module axi_sub_wr import axi_pkg::*; #(
     // Address Calculations                    //
     // --------------------------------------- //
     // Force aligned address to component
-    always_comb addr = {txn_ctx.addr[AW-1:BW],BW'(0)};
+    always_comb addr = {txn_ctx.addr[AW-1:0]};//,BW'(0)};
     always_comb user = txn_ctx.user;
     always_comb id   = txn_ctx.id;
 
@@ -296,19 +297,21 @@ module axi_sub_wr import axi_pkg::*; #(
         .OPT_OUTREG     (0   ),
         //
         .OPT_PASSTHROUGH(0   ),
-        .DW             (DW + BC + 1)
+        .DW             (DW + BC + 1 + 3)
     ) i_dp_skd (
         .i_clk  (clk             ),
         .i_reset(rst_n           ),
         .i_valid(txn_wvalid      ),
         .o_ready(txn_wready      ),
         .i_data ({s_axi_if.wdata,
                   s_axi_if.wstrb,
+                  txn_ctx.size,
                   s_axi_if.wlast}),
         .o_valid(dv_pre          ),
         .i_ready(!hld            ),
         .o_data ({wdata,
                   wstrb,
+                  wsize,
                   last }         )
     );