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libs: ahb_slv_sif: Latch hsize on address phase #502

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libs: ahb_slv_sif: Latch hsize on address phase #502

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8 changes: 5 additions & 3 deletions src/libs/rtl/ahb_slv_sif.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ module ahb_slv_sif
);

logic err_f;
logic [2:0] size;

localparam BITS_WDATA = $bits(wdata);

Expand All @@ -60,7 +61,7 @@ localparam BITS_WDATA = $bits(wdata);
generate
if ((AHB_DATA_WIDTH == 32) & (CLIENT_DATA_WIDTH == 32)) begin
always_comb begin
unique case (hsize_i) inside
unique case (size) inside
3'b000: //byte
//wdata = {{$bits(wdata)-8{1'b0}},hwdata_i[7:0]};
wdata = {{BITS_WDATA-8{1'b0}},hwdata_i[7:0]};
Expand All @@ -76,7 +77,7 @@ generate
always_comb hrdata_o = rdata;
end else if ((AHB_DATA_WIDTH == 64) & (CLIENT_DATA_WIDTH == 32)) begin
always_comb begin
unique case (hsize_i) inside
unique case (size) inside
3'b000: //byte
//wdata = addr[2] ? {{$bits(wdata)-8{1'b0}},hwdata_i[39:32]} : {{$bits(wdata)-8{1'b0}},hwdata_i[7:0]};
wdata = addr[2] ? {{BITS_WDATA-8{1'b0}},hwdata_i[39:32]} : {{BITS_WDATA-8{1'b0}},hwdata_i[7:0]};
Expand All @@ -92,7 +93,7 @@ generate
always_comb hrdata_o = addr[2] ? {rdata, 32'b0} : {32'b0, rdata};
end else if ((AHB_DATA_WIDTH == 64) & (CLIENT_DATA_WIDTH == 64)) begin
always_comb begin
unique case (hsize_i) inside
unique case (size) inside
3'b000: //byte
//wdata = {{$bits(wdata)-8{1'b0}},hwdata_i[7:0]};
wdata = {{BITS_WDATA-8{1'b0}},hwdata_i[7:0]};
Expand Down Expand Up @@ -127,6 +128,7 @@ endgenerate
if(hready_i & hsel_i) begin
addr <= haddr_i[CLIENT_ADDR_WIDTH-1:0];
write <= hwrite_i & |htrans_i;
size <= hsize_i;
end
end
end
Expand Down
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