mldsa keyvault implementation (#625)

* Integrate abr into 2.0

* Remove swap files

* Update with script

* UPdate name

* Revert reg files

* Add keygen+sign flow

* Fix typo

* Remove unnecessary isr defs

* Rerun rdl

* Exclude mldsa exe from license header check

* Update filelist

* Add adamsbridge as a submodule

* Fix typo

* temp changes

* stashing kv changes

* Fix mldsa encoding

* Update rdl and mldsa flows

* Update filelist

* Update submodule

* Fix typo

* undo comments

* Try increasing timeout for gdb tests

* Undo timeout change

* Update submodule

* stashing kv changes

* stashing keyvault changes for adamsbridge

* keyvault width increased to 512, number of entries decreased to 24
increased uds size to 512
keyvault variable write width for hmac 384/512
keyvault connection for adamsbridge implementation

* fixing merge

* removing files that shouldn't have been checked in

* updating ABR submodule

* file list updates

* MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mldsa_kv' with updated timestamp and hash after successful run

* fixing bad merge of script that included two function definitions of the same name

* MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/mldsa_kv' with updated timestamp and hash after successful run

---------

Co-authored-by: Kiran Upadhyayula <[email protected]>
Co-authored-by: Kiran Upadhyayula <[email protected]>
Co-authored-by: Michael Norris <“[email protected]”>

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-0aaee120d93ac18bc55c7839a4e4e1fc956b2f12d1d7b11850a42f0eb11914ba98c92368164c95e7a34e41a634c236f5
+357380de0b348b9d1a310e0b453f12722d1da13d675bd806fa1e56eea5d6d607e2014b012630990cf5415705cb926e63

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1730784274
+1731107556

src/doe/rtl/doe_fsm.sv

@@ -173,7 +173,7 @@ always_comb begin : kv_doe_fsm
             dest_write_en = '1;
             //increment dest offset each clock, clear when done
             dest_write_offset_en = '1;
-            dest_write_offset_nxt = (dest_write_offset == 'hb) ? 'h0 : dest_write_offset + 'd1;
+            dest_write_offset_nxt = dest_write_offset + 'd1;
 
             //go back to idle if dest done, and done with blocks
             if (arc_DOE_WRITE_DOE_DONE) kv_doe_fsm_ns = DOE_DONE;

src/doe/tb/doe_test_gen.py

@@ -73,10 +73,10 @@ def generate_doe_testvector():
     p = open("uds", "w")
     c = open("ciphertext", "w")
 
-    #key_str, iv_str, plain_str = generate_rand_bytes(32, 16, 48)
+    #key_str, iv_str, plain_str = generate_rand_bytes(32, 16, 64)
     key_str     = generate_rand_bytes(32)
     iv_str      = generate_rand_bytes(16)
-    plain_str   = generate_rand_bytes(48)
+    plain_str   = generate_rand_bytes(64)
     # key_str = "002ec695b21f27581a745c72e5b9f484865bc95eb10a13d584f57062166838d6"
     # iv_str = "a07b6cf2c26e78194b698f30ed0f5bdb"
     # plain_str = "754e68e5bdb5df41fca420e77655c76fe8ac8e4bc55727b2132bfdf9419a3b21b0dcc413c6f3f64a9b2d6cc1d861065b"

src/ecc/rtl/ecc_dsa_ctrl.sv

@@ -912,6 +912,7 @@ module ecc_dsa_ctrl
 
         //client control register
         .write_ctrl_reg(kv_write_ctrl_reg),
+        .num_dwords(REG_NUM_DWORDS[4:0]),
 
         //interface with kv
         .kv_write(kv_write),

src/ecc/rtl/ecc_reg.sv

@@ -344,7 +344,7 @@ module ecc_reg (
             struct packed{
                 logic next;
                 logic load_next;
-            } sha_block_dest_valid;
+            } mldsa_seed_dest_valid;
             struct packed{
                 logic next;
                 logic load_next;
@@ -587,7 +587,7 @@ module ecc_reg (
             } hmac_block_dest_valid;
             struct packed{
                 logic value;
-            } sha_block_dest_valid;
+            } mldsa_seed_dest_valid;
             struct packed{
                 logic value;
             } ecc_pkey_dest_valid;
@@ -1410,27 +1410,27 @@ module ecc_reg (
         end
     end
     assign hwif_out.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value;
-    // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid
+    // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid
     always_comb begin
         automatic logic [0:0] next_c;
         automatic logic load_next_c;
-        next_c = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value;
+        next_c = field_storage.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value;
         load_next_c = '0;
         if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write
-            next_c = (field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]);
+            next_c = (field_storage.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]);
             load_next_c = '1;
         end
-        field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.next = next_c;
-        field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.load_next = load_next_c;
+        field_combo.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.next = next_c;
+        field_combo.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.load_next = load_next_c;
     end
     always_ff @(posedge clk or negedge hwif_in.reset_b) begin
         if(~hwif_in.reset_b) begin
-            field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= 1'h0;
-        end else if(field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.load_next) begin
-            field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.next;
+            field_storage.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value <= 1'h0;
+        end else if(field_combo.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.load_next) begin
+            field_storage.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.next;
         end
     end
-    assign hwif_out.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value;
+    assign hwif_out.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value;
     // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid
     always_comb begin
         automatic logic [0:0] next_c;
@@ -1941,7 +1941,7 @@ module ecc_reg (
     assign readback_array[93][5:1] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value : '0;
     assign readback_array[93][6:6] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value : '0;
     assign readback_array[93][7:7] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value : '0;
-    assign readback_array[93][8:8] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value : '0;
+    assign readback_array[93][8:8] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.mldsa_seed_dest_valid.value : '0;
     assign readback_array[93][9:9] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value : '0;
     assign readback_array[93][10:10] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value : '0;
     assign readback_array[93][31:11] = (decoded_reg_strb.ecc_kv_wr_pkey_ctrl && !decoded_req_is_wr) ? field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value : '0;

src/ecc/rtl/ecc_reg_pkg.sv

@@ -400,7 +400,7 @@ package ecc_reg_pkg;
 
     typedef struct packed{
         logic value;
-    } kv_write_ctrl_reg__sha_block_dest_valid__out_t;
+    } kv_write_ctrl_reg__mldsa_seed_dest_valid__out_t;
 
     typedef struct packed{
         logic value;
@@ -419,7 +419,7 @@ package ecc_reg_pkg;
         kv_write_ctrl_reg__write_entry__out_t write_entry;
         kv_write_ctrl_reg__hmac_key_dest_valid__out_t hmac_key_dest_valid;
         kv_write_ctrl_reg__hmac_block_dest_valid__out_t hmac_block_dest_valid;
-        kv_write_ctrl_reg__sha_block_dest_valid__out_t sha_block_dest_valid;
+        kv_write_ctrl_reg__mldsa_seed_dest_valid__out_t mldsa_seed_dest_valid;
         kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid;
         kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid;
         kv_write_ctrl_reg__rsvd__out_t rsvd;

src/ecc/rtl/ecc_reg_uvm.sv

@@ -599,7 +599,7 @@ package ecc_reg_uvm;
         kv_write_ctrl_reg_bit_cg write_entry_bit_cg[5];
         kv_write_ctrl_reg_bit_cg hmac_key_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg hmac_block_dest_valid_bit_cg[1];
-        kv_write_ctrl_reg_bit_cg sha_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg mldsa_seed_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg ecc_pkey_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg ecc_seed_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg rsvd_bit_cg[21];
@@ -608,7 +608,7 @@ package ecc_reg_uvm;
         rand uvm_reg_field write_entry;
         rand uvm_reg_field hmac_key_dest_valid;
         rand uvm_reg_field hmac_block_dest_valid;
-        rand uvm_reg_field sha_block_dest_valid;
+        rand uvm_reg_field mldsa_seed_dest_valid;
         rand uvm_reg_field ecc_pkey_dest_valid;
         rand uvm_reg_field ecc_seed_dest_valid;
         rand uvm_reg_field rsvd;
@@ -631,8 +631,8 @@ package ecc_reg_uvm;
             this.hmac_key_dest_valid.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0);
             this.hmac_block_dest_valid = new("hmac_block_dest_valid");
             this.hmac_block_dest_valid.configure(this, 1, 7, "RW", 0, 'h0, 1, 1, 0);
-            this.sha_block_dest_valid = new("sha_block_dest_valid");
-            this.sha_block_dest_valid.configure(this, 1, 8, "RW", 0, 'h0, 1, 1, 0);
+            this.mldsa_seed_dest_valid = new("mldsa_seed_dest_valid");
+            this.mldsa_seed_dest_valid.configure(this, 1, 8, "RW", 0, 'h0, 1, 1, 0);
             this.ecc_pkey_dest_valid = new("ecc_pkey_dest_valid");
             this.ecc_pkey_dest_valid.configure(this, 1, 9, "RW", 0, 'h0, 1, 1, 0);
             this.ecc_seed_dest_valid = new("ecc_seed_dest_valid");
@@ -644,7 +644,7 @@ package ecc_reg_uvm;
                 foreach(write_entry_bit_cg[bt]) write_entry_bit_cg[bt] = new();
                 foreach(hmac_key_dest_valid_bit_cg[bt]) hmac_key_dest_valid_bit_cg[bt] = new();
                 foreach(hmac_block_dest_valid_bit_cg[bt]) hmac_block_dest_valid_bit_cg[bt] = new();
-                foreach(sha_block_dest_valid_bit_cg[bt]) sha_block_dest_valid_bit_cg[bt] = new();
+                foreach(mldsa_seed_dest_valid_bit_cg[bt]) mldsa_seed_dest_valid_bit_cg[bt] = new();
                 foreach(ecc_pkey_dest_valid_bit_cg[bt]) ecc_pkey_dest_valid_bit_cg[bt] = new();
                 foreach(ecc_seed_dest_valid_bit_cg[bt]) ecc_seed_dest_valid_bit_cg[bt] = new();
                 foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();

src/hmac/rtl/hmac.sv

@@ -410,6 +410,10 @@ hmac_block_kv_read
     .read_done(kv_block_done)
 );
 
+//write 512 or 384 result based on mode bit
+logic [$clog2(TAG_SIZE/32):0] num_dwords;
+always_comb num_dwords = mode_reg ? 'd16 : 'd12;
+
 //Write to keyvault
 kv_write_client #(
   .DATA_WIDTH(TAG_SIZE)
@@ -422,6 +426,7 @@ hmac_result_kv_write
 
   //client control register
   .write_ctrl_reg(kv_write_ctrl_reg),
+  .num_dwords(num_dwords), 
 
   //interface with kv
   .kv_write(kv_write),

src/hmac/rtl/hmac_reg.sv

@@ -280,7 +280,7 @@ module hmac_reg (
             struct packed{
                 logic next;
                 logic load_next;
-            } sha_block_dest_valid;
+            } mldsa_seed_dest_valid;
             struct packed{
                 logic next;
                 logic load_next;
@@ -570,7 +570,7 @@ module hmac_reg (
             } hmac_block_dest_valid;
             struct packed{
                 logic value;
-            } sha_block_dest_valid;
+            } mldsa_seed_dest_valid;
             struct packed{
                 logic value;
             } ecc_pkey_dest_valid;
@@ -1243,27 +1243,27 @@ module hmac_reg (
         end
     end
     assign hwif_out.HMAC512_KV_WR_CTRL.hmac_block_dest_valid.value = field_storage.HMAC512_KV_WR_CTRL.hmac_block_dest_valid.value;
-    // Field: hmac_reg.HMAC512_KV_WR_CTRL.sha_block_dest_valid
+    // Field: hmac_reg.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid
     always_comb begin
         automatic logic [0:0] next_c;
         automatic logic load_next_c;
-        next_c = field_storage.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value;
+        next_c = field_storage.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value;
         load_next_c = '0;
         if(decoded_reg_strb.HMAC512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write
-            next_c = (field_storage.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]);
+            next_c = (field_storage.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]);
             load_next_c = '1;
         end
-        field_combo.HMAC512_KV_WR_CTRL.sha_block_dest_valid.next = next_c;
-        field_combo.HMAC512_KV_WR_CTRL.sha_block_dest_valid.load_next = load_next_c;
+        field_combo.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.next = next_c;
+        field_combo.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.load_next = load_next_c;
     end
     always_ff @(posedge clk or negedge hwif_in.reset_b) begin
         if(~hwif_in.reset_b) begin
-            field_storage.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value <= 1'h0;
-        end else if(field_combo.HMAC512_KV_WR_CTRL.sha_block_dest_valid.load_next) begin
-            field_storage.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value <= field_combo.HMAC512_KV_WR_CTRL.sha_block_dest_valid.next;
+            field_storage.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value <= 1'h0;
+        end else if(field_combo.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.load_next) begin
+            field_storage.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value <= field_combo.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.next;
         end
     end
-    assign hwif_out.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value = field_storage.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value;
+    assign hwif_out.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value = field_storage.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value;
     // Field: hmac_reg.HMAC512_KV_WR_CTRL.ecc_pkey_dest_valid
     always_comb begin
         automatic logic [0:0] next_c;
@@ -2161,7 +2161,7 @@ module hmac_reg (
     assign readback_array[25][5:1] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.write_entry.value : '0;
     assign readback_array[25][6:6] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.hmac_key_dest_valid.value : '0;
     assign readback_array[25][7:7] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.hmac_block_dest_valid.value : '0;
-    assign readback_array[25][8:8] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.sha_block_dest_valid.value : '0;
+    assign readback_array[25][8:8] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.mldsa_seed_dest_valid.value : '0;
     assign readback_array[25][9:9] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.ecc_pkey_dest_valid.value : '0;
     assign readback_array[25][10:10] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.ecc_seed_dest_valid.value : '0;
     assign readback_array[25][31:11] = (decoded_reg_strb.HMAC512_KV_WR_CTRL && !decoded_req_is_wr) ? field_storage.HMAC512_KV_WR_CTRL.rsvd.value : '0;

src/hmac/rtl/hmac_reg_pkg.sv

@@ -248,7 +248,7 @@ package hmac_reg_pkg;
 
     typedef struct packed{
         logic value;
-    } kv_write_ctrl_reg__sha_block_dest_valid__out_t;
+    } kv_write_ctrl_reg__mldsa_seed_dest_valid__out_t;
 
     typedef struct packed{
         logic value;
@@ -267,7 +267,7 @@ package hmac_reg_pkg;
         kv_write_ctrl_reg__write_entry__out_t write_entry;
         kv_write_ctrl_reg__hmac_key_dest_valid__out_t hmac_key_dest_valid;
         kv_write_ctrl_reg__hmac_block_dest_valid__out_t hmac_block_dest_valid;
-        kv_write_ctrl_reg__sha_block_dest_valid__out_t sha_block_dest_valid;
+        kv_write_ctrl_reg__mldsa_seed_dest_valid__out_t mldsa_seed_dest_valid;
         kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid;
         kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid;
         kv_write_ctrl_reg__rsvd__out_t rsvd;

src/hmac/rtl/hmac_reg_uvm.sv

@@ -364,7 +364,7 @@ package hmac_reg_uvm;
         kv_write_ctrl_reg_bit_cg write_entry_bit_cg[5];
         kv_write_ctrl_reg_bit_cg hmac_key_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg hmac_block_dest_valid_bit_cg[1];
-        kv_write_ctrl_reg_bit_cg sha_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg mldsa_seed_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg ecc_pkey_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg ecc_seed_dest_valid_bit_cg[1];
         kv_write_ctrl_reg_bit_cg rsvd_bit_cg[21];
@@ -373,7 +373,7 @@ package hmac_reg_uvm;
         rand uvm_reg_field write_entry;
         rand uvm_reg_field hmac_key_dest_valid;
         rand uvm_reg_field hmac_block_dest_valid;
-        rand uvm_reg_field sha_block_dest_valid;
+        rand uvm_reg_field mldsa_seed_dest_valid;
         rand uvm_reg_field ecc_pkey_dest_valid;
         rand uvm_reg_field ecc_seed_dest_valid;
         rand uvm_reg_field rsvd;
@@ -396,8 +396,8 @@ package hmac_reg_uvm;
             this.hmac_key_dest_valid.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0);
             this.hmac_block_dest_valid = new("hmac_block_dest_valid");
             this.hmac_block_dest_valid.configure(this, 1, 7, "RW", 0, 'h0, 1, 1, 0);
-            this.sha_block_dest_valid = new("sha_block_dest_valid");
-            this.sha_block_dest_valid.configure(this, 1, 8, "RW", 0, 'h0, 1, 1, 0);
+            this.mldsa_seed_dest_valid = new("mldsa_seed_dest_valid");
+            this.mldsa_seed_dest_valid.configure(this, 1, 8, "RW", 0, 'h0, 1, 1, 0);
             this.ecc_pkey_dest_valid = new("ecc_pkey_dest_valid");
             this.ecc_pkey_dest_valid.configure(this, 1, 9, "RW", 0, 'h0, 1, 1, 0);
             this.ecc_seed_dest_valid = new("ecc_seed_dest_valid");
@@ -409,7 +409,7 @@ package hmac_reg_uvm;
                 foreach(write_entry_bit_cg[bt]) write_entry_bit_cg[bt] = new();
                 foreach(hmac_key_dest_valid_bit_cg[bt]) hmac_key_dest_valid_bit_cg[bt] = new();
                 foreach(hmac_block_dest_valid_bit_cg[bt]) hmac_block_dest_valid_bit_cg[bt] = new();
-                foreach(sha_block_dest_valid_bit_cg[bt]) sha_block_dest_valid_bit_cg[bt] = new();
+                foreach(mldsa_seed_dest_valid_bit_cg[bt]) mldsa_seed_dest_valid_bit_cg[bt] = new();
                 foreach(ecc_pkey_dest_valid_bit_cg[bt]) ecc_pkey_dest_valid_bit_cg[bt] = new();
                 foreach(ecc_seed_dest_valid_bit_cg[bt]) ecc_seed_dest_valid_bit_cg[bt] = new();
                 foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();