Merge pull request #3947 from alainmarcel/alainmarcel-patch-1

vpiSigned property on vars, typespec ignored by synlig
chipsalliance · Dec 27, 2023 · f1e9d4d · f1e9d4d
2 parents 2f3b7aa + 65838fa
commit f1e9d4d
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Showing 44 changed files with 122 additions and 6 deletions.
diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp
@@ -2280,6 +2280,14 @@ bool CompileHelper::compileDataDeclaration(
       NodeId intVec_TypeReg = fC->Child(data_type);
       if (fC->Type(intVec_TypeReg) == VObjectType::paVIRTUAL)
         intVec_TypeReg = fC->Sibling(intVec_TypeReg);
+      if (fC->Type(intVec_TypeReg) == VObjectType::paIntegerAtomType_Byte ||
+          fC->Type(intVec_TypeReg) == VObjectType::paIntegerAtomType_Int ||
+          fC->Type(intVec_TypeReg) == VObjectType::paIntegerAtomType_Integer ||
+          fC->Type(intVec_TypeReg) == VObjectType::paIntegerAtomType_LongInt ||
+          fC->Type(intVec_TypeReg) == VObjectType::paIntegerAtomType_Shortint ||
+          fC->Type(intVec_TypeReg) == VObjectType::paReal_number) {
+        is_signed = true;
+      }
       NodeId packedDimension = fC->Sibling(intVec_TypeReg);
       if (fC->Type(packedDimension) == VObjectType::slStringConst) {
         // class or package name;
@@ -2294,6 +2302,7 @@ bool CompileHelper::compileDataDeclaration(
         packedDimension = fC->Sibling(packedDimension);
       } else if (fC->Type(packedDimension) == VObjectType::paSigning_Unsigned) {
         packedDimension = fC->Sibling(packedDimension);
+        is_signed = false;
       }
       NodeId unpackedDimension;
       NodeId list_of_variable_decl_assignments = fC->Sibling(data_type);
@@ -3486,7 +3495,8 @@ bool CompileHelper::compileParameterDeclaration(
             type == VObjectType::paIntegerAtomType_Int ||
             type == VObjectType::paIntegerAtomType_Integer ||
             type == VObjectType::paIntegerAtomType_LongInt ||
-            type == VObjectType::paIntegerAtomType_Shortint) {
+            type == VObjectType::paIntegerAtomType_Shortint ||
+            type == VObjectType::paReal_number) {
           isSigned = true;
         }
         if (fC->Type(Signage) == VObjectType::paSigning_Signed) isSigned = true;

diff --git a/tests/AlwaysNoElab/AlwaysNoElab.log b/tests/AlwaysNoElab/AlwaysNoElab.log
@@ -1168,6 +1168,7 @@ design: (work@dut)
       \_int_typespec: , line:7:3, endln:7:6
     |vpiName:device
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_constant: , line:7:16, endln:7:17

diff --git a/tests/ArrayMethodIterator/ArrayMethodIterator.log b/tests/ArrayMethodIterator/ArrayMethodIterator.log
@@ -254,6 +254,7 @@ design: (work@top)
         \_int_typespec: , line:7:4, endln:7:7
       |vpiName:get_inst_id
       |vpiFullName:pkg::uvm_callback::get_inst_id
+      |vpiSigned:1
       |vpiAutomatic:1
       |vpiVisibility:1
   |vpiClassDefn:
@@ -647,6 +648,7 @@ design: (work@top)
     \_int_typespec: , line:7:4, endln:7:7
   |vpiName:get_inst_id
   |vpiFullName:pkg::uvm_callback::get_inst_id
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 \_class_typespec: (pkg::uvm_callbacks), line:29:1, endln:29:6

diff --git a/tests/AssociativeArray/AssociativeArray.log b/tests/AssociativeArray/AssociativeArray.log
@@ -233,6 +233,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:a
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:3
@@ -262,6 +263,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:b
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:3

diff --git a/tests/BindMethod/BindMethod.log b/tests/BindMethod/BindMethod.log
@@ -397,6 +397,7 @@ design: (unnamed)
           \_int_typespec: , line:10:3, endln:10:6
         |vpiName:fname
         |vpiFullName:uvm::uvm_vreg_field_cbs::fname
+        |vpiSigned:1
         |vpiAutomatic:1
         |vpiVisibility:1
       |vpiExtends:
@@ -522,6 +523,7 @@ design: (unnamed)
     \_int_typespec: , line:10:3, endln:10:6
   |vpiName:fname
   |vpiFullName:uvm::uvm_vreg_field_cbs::fname
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 ===================

diff --git a/tests/Bindings/Bindings.log b/tests/Bindings/Bindings.log
@@ -3494,6 +3494,7 @@ design: (work@dut1)
       \_int_typespec: , line:26:3, endln:26:6
     |vpiName:device
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_constant: , line:26:16, endln:26:17

diff --git a/tests/BlackBox/BlackBox.log b/tests/BlackBox/BlackBox.log
@@ -353,6 +353,7 @@ design: (work@top)
               \_int_typespec: , line:7:1, endln:7:4
             |vpiName:wb_writeback_en
             |vpiFullName:[email protected]_gen[0].core.wb_writeback_en
+            |vpiSigned:1
             |vpiVisibility:1
             |vpiInstance:
             \_module_inst: work@core ([email protected]_gen[0].core), file:${SURELOG_DIR}/tests/BlackBox/dut.sv, line:18:13, endln:18:26
@@ -425,6 +426,7 @@ design: (work@top)
     \_int_typespec: , line:7:1, endln:7:4
   |vpiName:wb_writeback_en
   |vpiFullName:[email protected]_gen[0].core.wb_writeback_en
+  |vpiSigned:1
   |vpiVisibility:1
 \_int_typespec: , line:7:1, endln:7:4
   |vpiSigned:1

diff --git a/tests/BuiltInMethod/BuiltInMethod.log b/tests/BuiltInMethod/BuiltInMethod.log
@@ -273,6 +273,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:b
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiExpr:
@@ -326,6 +327,7 @@ design: (work@top)
       \_byte_typespec: , line:3:5, endln:3:9
     |vpiName:o
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_hier_path: (b), line:3:14, endln:3:19
@@ -358,6 +360,7 @@ design: (work@top)
       \_byte_typespec: , line:4:5, endln:4:9
     |vpiName:o
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_hier_path: (b), line:4:14, endln:4:18
@@ -390,6 +393,7 @@ design: (work@top)
       \_byte_typespec: , line:5:5, endln:5:9
     |vpiName:o
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_hier_path: (b), line:5:14, endln:5:19
@@ -422,6 +426,7 @@ design: (work@top)
       \_byte_typespec: , line:6:5, endln:6:9
     |vpiName:o
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_hier_path: (b), line:6:14, endln:6:22

diff --git a/tests/CastTypespec/CastTypespec.log b/tests/CastTypespec/CastTypespec.log
@@ -2384,6 +2384,7 @@ design: (work@tlul_adapter_host)
       \_int_typespec: , line:28:5, endln:28:8
     |vpiName:a
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiVariables:
   \_int_var: ([email protected]), line:28:11, endln:28:12
@@ -2398,6 +2399,7 @@ design: (work@tlul_adapter_host)
       \_int_typespec: , line:28:5, endln:28:8
     |vpiName:b
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiVariables:
   \_int_var: ([email protected]), line:28:13, endln:28:14
@@ -2412,6 +2414,7 @@ design: (work@tlul_adapter_host)
       \_int_typespec: , line:28:5, endln:28:8
     |vpiName:c
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiParameter:
   \_parameter: ([email protected]), line:35:14, endln:35:24

diff --git a/tests/ClassFuncTask/ClassFuncTask.log b/tests/ClassFuncTask/ClassFuncTask.log
@@ -110,6 +110,7 @@ design: (unnamed)
         \_int_typespec: , line:13:3, endln:13:6
       |vpiName:x
       |vpiFullName:pack::C::x
+      |vpiSigned:1
       |vpiAutomatic:1
       |vpiVisibility:1
     |vpiParameter:
@@ -485,6 +486,7 @@ design: (unnamed)
     \_int_typespec: , line:13:3, endln:13:6
   |vpiName:x
   |vpiFullName:pack::C::x
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 \_bit_typespec: , line:6:3, endln:6:18

diff --git a/tests/ClassMethodCall/ClassMethodCall.log b/tests/ClassMethodCall/ClassMethodCall.log
@@ -122,6 +122,7 @@ design: (work@door_mod)
         \_int_typespec: , line:6:5, endln:6:8
       |vpiName:state
       |vpiFullName:pack::door::state
+      |vpiSigned:1
       |vpiAutomatic:1
       |vpiVisibility:1
     |vpiVariables:
@@ -137,6 +138,7 @@ design: (work@door_mod)
         \_int_typespec: , line:7:5, endln:7:8
       |vpiName:timer
       |vpiFullName:pack::door::timer
+      |vpiSigned:1
       |vpiAutomatic:1
       |vpiVisibility:1
     |vpiVariables:
@@ -817,6 +819,7 @@ design: (work@door_mod)
     \_int_typespec: , line:6:5, endln:6:8
   |vpiName:state
   |vpiFullName:pack::door::state
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 \_int_typespec: , line:7:5, endln:7:8
@@ -835,6 +838,7 @@ design: (work@door_mod)
     \_int_typespec: , line:7:5, endln:7:8
   |vpiName:timer
   |vpiFullName:pack::door::timer
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 \_logic_typespec: , line:8:5, endln:8:10

diff --git a/tests/ClassMini/ClassMini.log b/tests/ClassMini/ClassMini.log
@@ -113,6 +113,7 @@ design: (work@door_mod)
         \_int_typespec: , line:4:5, endln:4:8
       |vpiName:state
       |vpiFullName:pack::door::state
+      |vpiSigned:1
       |vpiAutomatic:1
       |vpiVisibility:1
     |vpiVariables:
@@ -128,6 +129,7 @@ design: (work@door_mod)
         \_int_typespec: , line:5:5, endln:5:8
       |vpiName:timer
       |vpiFullName:pack::door::timer
+      |vpiSigned:1
       |vpiAutomatic:1
       |vpiVisibility:1
     |vpiVariables:
@@ -562,6 +564,7 @@ design: (work@door_mod)
     \_int_typespec: , line:4:5, endln:4:8
   |vpiName:state
   |vpiFullName:pack::door::state
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 \_int_typespec: , line:5:5, endln:5:8
@@ -580,6 +583,7 @@ design: (work@door_mod)
     \_int_typespec: , line:5:5, endln:5:8
   |vpiName:timer
   |vpiFullName:pack::door::timer
+  |vpiSigned:1
   |vpiAutomatic:1
   |vpiVisibility:1
 \_logic_typespec: , line:6:5, endln:6:10

diff --git a/tests/DelayAssign/DelayAssign.log b/tests/DelayAssign/DelayAssign.log
@@ -2485,6 +2485,7 @@ design: (work@SimDTM)
       \_int_typespec: , line:42:3, endln:42:6
     |vpiName:__debug_req_bits_addr
     |vpiFullName:work@SimDTM.__debug_req_bits_addr
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiVariables:
   \_int_var: (work@SimDTM.__debug_req_bits_op), line:43:7, endln:43:26
@@ -2499,6 +2500,7 @@ design: (work@SimDTM)
       \_int_typespec: , line:43:3, endln:43:6
     |vpiName:__debug_req_bits_op
     |vpiFullName:work@SimDTM.__debug_req_bits_op
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiVariables:
   \_int_var: (work@SimDTM.__debug_req_bits_data), line:44:7, endln:44:28
@@ -2513,6 +2515,7 @@ design: (work@SimDTM)
       \_int_typespec: , line:44:3, endln:44:6
     |vpiName:__debug_req_bits_data
     |vpiFullName:work@SimDTM.__debug_req_bits_data
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiVariables:
   \_bit_var: (work@SimDTM.__debug_resp_ready), line:45:7, endln:45:25
@@ -2541,6 +2544,7 @@ design: (work@SimDTM)
       \_int_typespec: , line:46:3, endln:46:6
     |vpiName:__exit
     |vpiFullName:work@SimDTM.__exit
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiDefName:work@SimDTM
   |vpiTop:1

diff --git a/tests/DollarRoot/DollarRoot.log b/tests/DollarRoot/DollarRoot.log
@@ -17509,6 +17509,7 @@ design: (work@top)
       \_int_typespec: , line:332:4, endln:332:7
     |vpiName:pending_read_cycles_slave_0
     |vpiFullName:work@test_program.pending_read_cycles_slave_0
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_constant: , line:332:38, endln:332:39
@@ -17531,6 +17532,7 @@ design: (work@top)
       \_int_typespec: , line:475:4, endln:475:7
     |vpiName:pending_read_cycles_slave_1
     |vpiFullName:work@test_program.pending_read_cycles_slave_1
+    |vpiSigned:1
     |vpiVisibility:1
     |vpiExpr:
     \_constant: , line:475:38, endln:475:39

diff --git a/tests/DynArrayKind/DynArrayKind.log b/tests/DynArrayKind/DynArrayKind.log
@@ -319,6 +319,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:dynamic1
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:2
@@ -348,6 +349,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:dynamic2
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:2
@@ -397,6 +399,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:dynamic3
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:2
@@ -414,6 +417,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:dynamic4
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:2
@@ -431,6 +435,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:assoc
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:3
@@ -460,6 +465,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:assoc_string
     |vpiFullName:[email protected]_string
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:3
@@ -489,6 +495,7 @@ design: (work@top)
       \_array_typespec: 
     |vpiName:queue
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiRandType:1
     |vpiVisibility:1
     |vpiArrayType:4

diff --git a/tests/EnumConstElab/EnumConstElab.log b/tests/EnumConstElab/EnumConstElab.log
@@ -854,6 +854,7 @@ design: (work@top)
           \_int_typespec: , line:3:4, endln:3:7
         |vpiName:a
         |vpiFullName:[email protected]_ctrl_reg_shadowed.staged_reg.a
+        |vpiSigned:1
         |vpiVisibility:1
         |vpiExpr:
         \_operation: , line:3:12, endln:3:24

diff --git a/tests/ForLoop/ForLoop.log b/tests/ForLoop/ForLoop.log
@@ -3091,6 +3091,7 @@ design: (work@t)
       \_integer_typespec: , line:3:3, endln:3:10
     |vpiName:a
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiVariables:
   \_integer_var: ([email protected]), line:3:14, endln:3:15
@@ -3105,6 +3106,7 @@ design: (work@t)
       \_integer_typespec: , line:3:3, endln:3:10
     |vpiName:b
     |vpiFullName:[email protected]
+    |vpiSigned:1
     |vpiVisibility:1
   |vpiDefName:work@t
   |vpiTop:1