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Merge pull request #3944 from alainmarcel/alainmarcel-patch-1
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allModules and topModules vpiAlways sorting
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@alaindargelas
alaindargelas authored Dec 18, 2023
2 parents 971dc26 + 587f54e commit b0c68fb
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Showing 4 changed files with 220 additions and 217 deletions.
120 changes: 120 additions & 0 deletions src/DesignCompile/UhdmWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4527,6 +4527,125 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance,
}
}


class AlwaysWithForLoop : public VpiListener {
public:
explicit AlwaysWithForLoop() {}
~AlwaysWithForLoop() override = default;
void leaveFor_stmt(const for_stmt* object, vpiHandle handle) {
containtsForStmt = true;
}
bool containtsForStmt = false;
};

bool alwaysContainsForLoop(Serializer& serializer, any* root) {
AlwaysWithForLoop* listener = new AlwaysWithForLoop();
vpiHandle handle = serializer.MakeUhdmHandle(root->UhdmType(), root);
listener->listenAny(handle);
vpi_release_handle(handle);
bool result = listener->containtsForStmt;
delete listener;
return result;
}

// synlig has a major problem processing always blocks.
// They are processed mainly in the allModules section which is incorrect in some case.
// They should be processed from the topModules section.
// Here we try to fix temporarily this by filtering out the always blocks containing for-loops
// from the allModules, and those without from the topModules
void filterAlwaysBlocks(Serializer& s, design* d) {
if (d->AllModules()) {
for (auto module : *d->AllModules()) {
if (module->Process()) {
bool more = true;
while (more) {
more = false;
for (std::vector<process_stmt*>::iterator itr =
module->Process()->begin();
itr != module->Process()->end(); itr++) {
if ((*itr)->UhdmType() == uhdmalways) {
if (alwaysContainsForLoop(s, (*itr))) {
more = true;
module->Process()->erase(itr);
break;
}
}
}
}
}
}
}
std::queue<scope*> instances;
if (d->TopModules()) {
for (auto mod : *d->TopModules()) {
instances.push(mod) ;
}
}
while (!instances.empty()) {
scope* current = instances.front();
instances.pop();
if (current->UhdmType() == uhdmmodule_inst) {
module_inst* mod = (module_inst*) current;
if (mod->Process()) {
bool more = true;
while (more) {
more = false;
for (std::vector<process_stmt*>::iterator itr =
mod->Process()->begin();
itr != mod->Process()->end(); itr++) {
if ((*itr)->UhdmType() == uhdmalways) {
if (!alwaysContainsForLoop(s, (*itr))) {
more = true;
mod->Process()->erase(itr);
break;
}
}
}
}
}
if (mod->Modules()) {
for (auto m : *mod->Modules()) {
instances.push(m);
}
}
if (mod->Gen_scope_arrays()) {
for (auto m : *mod->Gen_scope_arrays()) {
instances.push(m->Gen_scopes()->at(0));
}
}
} else if (current->UhdmType() == uhdmgen_scope) {
gen_scope* sc = (gen_scope*) current;
if (sc->Process()) {
bool more = true;
while (more) {
more = false;
for (std::vector<process_stmt*>::iterator itr =
sc->Process()->begin();
itr != sc->Process()->end(); itr++) {
if ((*itr)->UhdmType() == uhdmalways) {
if (!alwaysContainsForLoop(s, (*itr))) {
more = true;
sc->Process()->erase(itr);
break;
}
}
}
}
}
if (sc->Modules()) {
for (auto m : *sc->Modules()) {
instances.push(m);
}
}
if (sc->Gen_scope_arrays()) {
for (auto m : *sc->Gen_scope_arrays()) {
instances.push(m->Gen_scopes()->at(0));
}
}
}
}
}

vpiHandle UhdmWriter::write(PathId uhdmFileId) {
FileSystem* const fileSystem = FileSystem::getInstance();
ModPortMap modPortMap;
Expand Down Expand Up @@ -4966,6 +5085,7 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) {
annotate->listenDesigns(designs);
annotate->filterNonSynthesizable();
delete annotate;
filterAlwaysBlocks(s, d);
}
}

Expand Down
190 changes: 93 additions & 97 deletions tests/3SigsSensList/3SigsSensList.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -517,94 +517,6 @@ design: (work@dut)
\_logic_typespec: , line:5:7, endln:5:11
|vpiInstance:
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/3SigsSensList/dut.sv, line:1:1, endln:36:10
|vpiProcess:
\_always: , line:24:1, endln:34:4
|vpiParent:
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/3SigsSensList/dut.sv, line:1:1, endln:36:10
|vpiStmt:
\_event_control: , line:24:8, endln:24:55
|vpiParent:
\_always: , line:24:1, endln:34:4
|vpiCondition:
\_operation: , line:24:11, endln:24:54
|vpiParent:
\_event_control: , line:24:8, endln:24:55
|vpiOpType:35
|vpiOperand:
\_operation: , line:24:11, endln:24:22
|vpiParent:
\_operation: , line:24:11, endln:24:37
|vpiOpType:39
|vpiOperand:
\_ref_obj: ([email protected]), line:24:19, endln:24:22
|vpiParent:
\_operation: , line:24:11, endln:24:22
|vpiName:clk
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:3:18, endln:3:21
|vpiOperand:
\_operation: , line:24:41, endln:24:54
|vpiParent:
\_operation: , line:24:11, endln:24:54
|vpiOpType:39
|vpiOperand:
\_ref_obj: (synlig_tmp_rst_or_start)
|vpiName:synlig_tmp_rst_or_start
|vpiActual:
\_logic_net: (synlig_tmp_rst_or_start)
|vpiStmt:
\_begin: (work@dut), line:25:1, endln:34:4
|vpiParent:
\_event_control: , line:24:8, endln:24:55
|vpiFullName:work@dut
|vpiStmt:
\_if_else: , line:26:2, endln:33:5
|vpiParent:
\_begin: (work@dut), line:25:1, endln:34:4
|vpiCondition:
\_ref_obj: (synlig_tmp_rst_or_start)
|vpiStmt:
\_begin: (work@dut), line:27:2, endln:29:5
|vpiParent:
\_if_else: , line:26:2, endln:33:5
|vpiFullName:work@dut
|vpiStmt:
\_assignment: , line:28:4, endln:28:19
|vpiParent:
\_begin: (work@dut), line:27:2, endln:29:5
|vpiOpType:82
|vpiRhs:
\_constant: , line:28:18, endln:28:19
|vpiLhs:
\_ref_obj: ([email protected]), line:28:4, endln:28:14
|vpiParent:
\_assignment: , line:28:4, endln:28:19
|vpiName:outputLine
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:28:4, endln:28:14
|vpiElseStmt:
\_begin: (work@dut), line:31:2, endln:33:5
|vpiParent:
\_if_else: , line:26:2, endln:33:5
|vpiFullName:work@dut
|vpiStmt:
\_assignment: , line:32:3, endln:32:24
|vpiParent:
\_begin: (work@dut), line:31:2, endln:33:5
|vpiOpType:82
|vpiRhs:
\_constant: , line:32:23, endln:32:24
|vpiLhs:
\_ref_obj: ([email protected]), line:32:3, endln:32:19
|vpiParent:
\_assignment: , line:32:3, endln:32:24
|vpiName:yScaleAmountNext
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:32:3, endln:32:19
|vpiAlwaysType:1
|vpiContAssign:
\_cont_assign:
|vpiRhs:
Expand Down Expand Up @@ -657,30 +569,114 @@ design: (work@dut)
\_logic_typespec: , line:3:7, endln:3:11
\_logic_typespec: , line:4:7, endln:4:11
\_logic_typespec: , line:5:7, endln:5:11
\_operation: , line:24:26, endln:24:37
|vpiParent:
\_operation: , line:24:11, endln:24:37
|vpiOpType:39
|vpiOperand:
\_ref_obj: ([email protected]), line:24:34, endln:24:37
\_operation: , line:24:11, endln:24:37
|vpiParent:
\_operation: , line:24:11, endln:24:54
|vpiOpType:35
|vpiOperand:
\_operation: , line:24:11, endln:24:22
\_operation: , line:24:26, endln:24:37
|vpiParent:
\_operation: , line:24:11, endln:24:37
|vpiOpType:39
|vpiOperand:
\_ref_obj: ([email protected]), line:24:19, endln:24:22
|vpiParent:
\_operation: , line:24:11, endln:24:22
|vpiName:clk
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:3:18, endln:3:21
\_operation: , line:24:11, endln:24:54
|vpiParent:
\_operation: , line:24:11, endln:24:37
|vpiOpType:39
\_event_control: , line:24:8, endln:24:55
|vpiOpType:35
|vpiOperand:
\_ref_obj: ([email protected]), line:24:34, endln:24:37
\_operation: , line:24:11, endln:24:22
|vpiOperand:
\_operation: , line:24:41, endln:24:54
|vpiParent:
\_operation: , line:24:11, endln:24:54
|vpiOpType:39
|vpiOperand:
\_ref_obj: (synlig_tmp_rst_or_start)
|vpiName:synlig_tmp_rst_or_start
|vpiActual:
\_logic_net: (synlig_tmp_rst_or_start)
\_event_control: , line:24:8, endln:24:55
|vpiParent:
\_always: , line:24:1, endln:34:4
|vpiCondition:
\_operation: , line:24:11, endln:24:54
|vpiStmt:
\_begin: (work@dut), line:25:1, endln:34:4
|vpiParent:
\_event_control: , line:24:8, endln:24:55
|vpiFullName:work@dut
|vpiStmt:
\_if_else: , line:26:2, endln:33:5
|vpiParent:
\_begin: (work@dut), line:25:1, endln:34:4
|vpiCondition:
\_ref_obj: (synlig_tmp_rst_or_start)
|vpiStmt:
\_begin: (work@dut), line:27:2, endln:29:5
|vpiParent:
\_if_else: , line:26:2, endln:33:5
|vpiFullName:work@dut
|vpiStmt:
\_assignment: , line:28:4, endln:28:19
|vpiParent:
\_begin: (work@dut), line:27:2, endln:29:5
|vpiOpType:82
|vpiRhs:
\_constant: , line:28:18, endln:28:19
|vpiLhs:
\_ref_obj: ([email protected]), line:28:4, endln:28:14
|vpiParent:
\_assignment: , line:28:4, endln:28:19
|vpiName:outputLine
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:28:4, endln:28:14
|vpiElseStmt:
\_begin: (work@dut), line:31:2, endln:33:5
|vpiParent:
\_if_else: , line:26:2, endln:33:5
|vpiFullName:work@dut
|vpiStmt:
\_assignment: , line:32:3, endln:32:24
|vpiParent:
\_begin: (work@dut), line:31:2, endln:33:5
|vpiOpType:82
|vpiRhs:
\_constant: , line:32:23, endln:32:24
|vpiLhs:
\_ref_obj: ([email protected]), line:32:3, endln:32:19
|vpiParent:
\_assignment: , line:32:3, endln:32:24
|vpiName:yScaleAmountNext
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: ([email protected]), line:32:3, endln:32:19
\_always: , line:24:1, endln:34:4
|vpiParent:
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/3SigsSensList/dut.sv, line:1:1, endln:36:10
|vpiStmt:
\_event_control: , line:24:8, endln:24:55
|vpiAlwaysType:1
===================
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 2
[WARNING] : 0
[ NOTE] : 5

============================== Begin Linting Results ==============================
[LINT]: ${SURELOG_DIR}/tests/3SigsSensList/dut.sv:28:4: Illegal wire LHS, outputLine
[LINT]: ${SURELOG_DIR}/tests/3SigsSensList/dut.sv:32:3: Illegal wire LHS, yScaleAmountNext
============================== End Linting Results ==============================

============================== Begin RoundTrip Results ==============================
[roundtrip]: ${SURELOG_DIR}/tests/3SigsSensList/dut.sv | ${SURELOG_DIR}/build/regression/3SigsSensList/roundtrip/dut_000.sv | 20 | 36 |
============================== End RoundTrip Results ==============================
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