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Merge pull request #3932 from alainmarcel/alainmarcel-patch-1
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hier path simplification
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@alaindargelas
alaindargelas authored Dec 9, 2023
2 parents 02876e4 + 9fa17d6 commit 83fa379
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Showing 12 changed files with 703 additions and 206 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/non_vendored.yml
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Expand Up @@ -58,7 +58,7 @@ jobs:
cmake -B build -DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_STANDARD=17 -DCMAKE_POSITION_INDEPENDENT_CODE=ON -DJSON_BuildTests=OFF . && cmake --build build && sudo cmake --install build
popd
git clone --depth 1 --branch v1.81 https://github.com/chipsalliance/UHDM.git
git clone --depth 1 --branch v1.82 https://github.com/chipsalliance/UHDM.git
pushd UHDM
cmake -B build -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DUHDM_USE_HOST_GTEST=ON -DUHDM_USE_HOST_CAPNP=ON . && cmake --build build && sudo cmake --install build
popd
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2 changes: 1 addition & 1 deletion .gitmodules
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Expand Up @@ -7,7 +7,7 @@
[submodule "third_party/UHDM"]
path = third_party/UHDM
url = https://github.com/chipsalliance/UHDM.git
branch = v1.81
branch = v1.82
[submodule "third_party/antlr4"]
path = third_party/antlr4
url = https://github.com/antlr/antlr4.git
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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Expand Up @@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
# Version changes whenever some new features accumulated, or the
# grammar or the cache format changes to make sure caches
# are invalidated.
project(SURELOG VERSION 1.81)
project(SURELOG VERSION 1.82)

# Detect build type, fallback to release and throw a warning if use didn't
# specify any
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64 changes: 3 additions & 61 deletions tests/ComplexHierPath/ComplexHierPath.log
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Expand Up @@ -651,31 +651,7 @@ design: (work@genblk_dive_top)
\_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39
|vpiName:B.x
|vpiLhs:
\_hier_path: (B.C.x), line:16:40, endln:16:45
|vpiParent:
\_cont_assign: , line:16:40, endln:16:51
|vpiActual:
\_ref_obj: (B), line:16:42, endln:16:43
|vpiParent:
\_hier_path: (B.C.x), line:16:40, endln:16:45
|vpiName:B
|vpiActual:
\_gen_scope: (work@genblk_dive_top.Z.A.B), line:7:40, endln:15:36
|vpiActual:
\_ref_obj: (C), line:16:42, endln:16:43
|vpiParent:
\_hier_path: (B.C.x), line:16:40, endln:16:45
|vpiName:C
|vpiActual:
\_gen_scope: (work@genblk_dive_top.Z.A.B.C), line:9:48, endln:13:44
|vpiActual:
\_ref_obj: (x), line:16:44, endln:16:45
|vpiParent:
\_hier_path: (B.C.x), line:16:40, endln:16:45
|vpiName:x
|vpiActual:
\_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39
|vpiName:B.C.x
\_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39
|vpiGenScopeArray:
\_gen_scope_array: (work@genblk_dive_top.Z.A.B), line:7:40, endln:15:36
|vpiParent:
Expand Down Expand Up @@ -740,24 +716,7 @@ design: (work@genblk_dive_top)
\_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47
|vpiName:A.B.C.x
|vpiLhs:
\_hier_path: (A.x), line:14:48, endln:14:51
|vpiParent:
\_cont_assign: , line:14:48, endln:14:61
|vpiActual:
\_ref_obj: (A), line:14:50, endln:14:51
|vpiParent:
\_hier_path: (A.x), line:14:48, endln:14:51
|vpiName:A
|vpiActual:
\_gen_scope: (work@genblk_dive_top.Z.A), line:5:32, endln:17:28
|vpiActual:
\_ref_obj: (x), line:14:50, endln:14:51
|vpiParent:
\_hier_path: (A.x), line:14:48, endln:14:51
|vpiName:x
|vpiActual:
\_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47
|vpiName:A.x
\_logic_net: (work@genblk_dive_top.Z.A.x), line:6:38, endln:6:39
|vpiGenScopeArray:
\_gen_scope_array: (work@genblk_dive_top.Z.A.B.C), line:9:48, endln:13:44
|vpiParent:
Expand Down Expand Up @@ -851,24 +810,7 @@ design: (work@genblk_dive_top)
|UINT:0
|vpiConstType:9
|vpiLhs:
\_hier_path: (B.x), line:11:56, endln:11:59
|vpiParent:
\_cont_assign: , line:11:56, endln:11:63
|vpiActual:
\_ref_obj: (B), line:11:58, endln:11:59
|vpiParent:
\_hier_path: (B.x), line:11:56, endln:11:59
|vpiName:B
|vpiActual:
\_gen_scope: (work@genblk_dive_top.Z.A.B), line:7:40, endln:15:36
|vpiActual:
\_ref_obj: (x), line:11:58, endln:11:59
|vpiParent:
\_hier_path: (B.x), line:11:56, endln:11:59
|vpiName:x
|vpiActual:
\_logic_net: (work@genblk_dive_top.Z.A.B.C.x), line:10:54, endln:10:55
|vpiName:B.x
\_logic_net: (work@genblk_dive_top.Z.A.B.x), line:8:46, endln:8:47
|vpiContAssign:
\_cont_assign: , line:20:16, endln:20:25
|vpiParent:
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25 changes: 1 addition & 24 deletions tests/DollarRoot/DollarRoot.log
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Expand Up @@ -17401,30 +17401,7 @@ design: (work@top)
|vpiActual:
\_logic_net: ([email protected]), line:1:25, endln:1:26
|vpiLhs:
\_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17
|vpiParent:
\_cont_assign: , line:2:11, endln:2:26
|vpiActual:
\_ref_obj: ($root), line:2:17, endln:2:20
|vpiParent:
\_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17
|vpiName:$root
|vpiActual:
\_ref_obj: (top), line:2:17, endln:2:20
|vpiParent:
\_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17
|vpiName:top
|vpiActual:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:1:1, endln:3:10
|vpiActual:
\_ref_obj: (a), line:2:21, endln:2:22
|vpiParent:
\_hier_path: (work@top.$root.top.a), line:2:11, endln:2:17
|vpiName:a
|vpiActual:
\_logic_net: ([email protected]), line:1:41, endln:1:42
|vpiName:$root.top.a
|vpiFullName:work@top.$root.top.a
\_logic_net: ([email protected]), line:1:41, endln:1:42
|uhdmtopModules:
\_module_inst: work@test_program (work@test_program), file:${SURELOG_DIR}/tests/DollarRoot/dut.sv, line:5:1, endln:797:10
|vpiName:work@test_program
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76 changes: 4 additions & 72 deletions tests/ImplicitGenBlock/ImplicitGenBlock.log
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Expand Up @@ -748,24 +748,7 @@ design: (work@top)
|vpiRhs:
\_constant: , line:66:28, endln:66:29
|vpiLhs:
\_hier_path: (genblk1.t), line:66:16, endln:66:25
|vpiParent:
\_cont_assign: , line:66:16, endln:66:29
|vpiActual:
\_ref_obj: (genblk1), line:66:24, endln:66:25
|vpiParent:
\_hier_path: (genblk1.t), line:66:16, endln:66:25
|vpiName:genblk1
|vpiActual:
\_gen_scope: ([email protected]), line:35:25, endln:35:32
|vpiActual:
\_ref_obj: (t), line:66:24, endln:66:25
|vpiParent:
\_hier_path: (genblk1.t), line:66:16, endln:66:25
|vpiName:t
|vpiActual:
\_logic_net: ([email protected]), line:35:30, endln:35:31
|vpiName:genblk1.t
\_logic_net: ([email protected]), line:35:30, endln:35:31
|vpiContAssign:
\_cont_assign: , line:67:16, endln:67:34
|vpiParent:
Expand Down Expand Up @@ -803,74 +786,23 @@ design: (work@top)
|vpiRhs:
\_constant: , line:68:28, endln:68:29
|vpiLhs:
\_hier_path: (genblk1.u), line:68:16, endln:68:25
|vpiParent:
\_cont_assign: , line:68:16, endln:68:29
|vpiActual:
\_ref_obj: (genblk1), line:68:24, endln:68:25
|vpiParent:
\_hier_path: (genblk1.u), line:68:16, endln:68:25
|vpiName:genblk1
|vpiActual:
\_gen_scope: ([email protected]), line:35:25, endln:35:32
|vpiActual:
\_ref_obj: (u), line:68:24, endln:68:25
|vpiParent:
\_hier_path: (genblk1.u), line:68:16, endln:68:25
|vpiName:u
|vpiActual:
\_logic_net: ([email protected]), line:47:30, endln:47:31
|vpiName:genblk1.u
\_logic_net: ([email protected]), line:47:30, endln:47:31
|vpiContAssign:
\_cont_assign: , line:69:16, endln:69:27
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10
|vpiRhs:
\_constant: , line:69:26, endln:69:27
|vpiLhs:
\_hier_path: (bar2.x2), line:69:16, endln:69:23
|vpiParent:
\_cont_assign: , line:69:16, endln:69:27
|vpiActual:
\_ref_obj: (bar2), line:69:21, endln:69:23
|vpiParent:
\_hier_path: (bar2.x2), line:69:16, endln:69:23
|vpiName:bar2
|vpiActual:
\_gen_scope: ([email protected]), line:53:17, endln:62:20
|vpiActual:
\_ref_obj: (x2), line:69:21, endln:69:23
|vpiParent:
\_hier_path: (bar2.x2), line:69:16, endln:69:23
|vpiName:x2
|vpiActual:
\_logic_net: ([email protected]), line:54:30, endln:54:32
|vpiName:bar2.x2
\_logic_net: ([email protected]), line:54:30, endln:54:32
|vpiContAssign:
\_cont_assign: , line:70:16, endln:70:27
|vpiParent:
\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ImplicitGenBlock/dut.sv, line:30:1, endln:74:10
|vpiRhs:
\_constant: , line:70:26, endln:70:27
|vpiLhs:
\_hier_path: (bar2.y2), line:70:16, endln:70:23
|vpiParent:
\_cont_assign: , line:70:16, endln:70:27
|vpiActual:
\_ref_obj: (bar2), line:70:21, endln:70:23
|vpiParent:
\_hier_path: (bar2.y2), line:70:16, endln:70:23
|vpiName:bar2
|vpiActual:
\_gen_scope: ([email protected]), line:53:17, endln:62:20
|vpiActual:
\_ref_obj: (y2), line:70:21, endln:70:23
|vpiParent:
\_hier_path: (bar2.y2), line:70:16, endln:70:23
|vpiName:y2
|vpiActual:
\_logic_net: ([email protected]), line:56:30, endln:56:32
|vpiName:bar2.y2
\_logic_net: ([email protected]), line:56:30, endln:56:32
|vpiContAssign:
\_cont_assign: , line:71:16, endln:71:31
|vpiParent:
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19 changes: 1 addition & 18 deletions tests/LocalScopeAssign/LocalScopeAssign.log
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Expand Up @@ -290,24 +290,7 @@ design: (work@module_scope_Example)
|vpiName:v2
|vpiFullName:work@module_scope_Example.v2
|vpiLhs:
\_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34
|vpiParent:
\_cont_assign: , line:7:11, endln:7:39
|vpiActual:
\_ref_obj: (module_scope_Example), line:7:32, endln:7:34
|vpiParent:
\_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34
|vpiName:module_scope_Example
|vpiActual:
\_module_inst: work@module_scope_Example (work@module_scope_Example), file:${SURELOG_DIR}/tests/LocalScopeAssign/dut.sv, line:3:1, endln:8:10
|vpiActual:
\_ref_obj: (o2), line:7:32, endln:7:34
|vpiParent:
\_hier_path: (module_scope_Example.o2), line:7:11, endln:7:34
|vpiName:o2
|vpiActual:
\_logic_net: (work@module_scope_Example.o2), line:3:33, endln:3:35
|vpiName:module_scope_Example.o2
\_logic_net: (work@module_scope_Example.o2), line:3:33, endln:3:35
\_weaklyReferenced:
\_logic_typespec: , line:4:11, endln:4:22
|vpiRange:
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