Merge pull request #3909 from alainmarcel/alainmarcel-patch-1

Report first 10 syntax errors per file
chipsalliance · Oct 17, 2023 · 6b20406 · 6b20406
2 parents 1a5ca24 + 8a9d67e
commit 6b20406
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Showing 13 changed files with 1,394 additions and 179 deletions.
diff --git a/.vscode/launch.json b/.vscode/launch.json
@@ -837,7 +837,7 @@
             "type": "cppdbg",
             "request": "launch",
             "program": "${workspaceFolder}/dbuild/bin/surelog",
-            "args": ["-parse", "tests/ScratchPad.sv", "-elabuhdm",  "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nocache", "-nobuiltin"],
+            "args": ["-parse", "tests/ScratchPad.sv", "-elabuhdm",  "-d", "inst", "-synth", "-d", "ast", "-d", "uhdm", "-d", "uhdmstats", "-d", "vpi_ids", "-replay", "-nobuiltin"],
             "stopAtEntry": false,
             "cwd": "${workspaceFolder}",
             "environment": [],

diff --git a/include/Surelog/SourceCompile/AntlrParserErrorListener.h b/include/Surelog/SourceCompile/AntlrParserErrorListener.h
@@ -40,7 +40,7 @@ class AntlrParserErrorListener : public antlr4::ANTLRErrorListener {
   AntlrParserErrorListener(ParseFile *parser, bool watchDogOn,
                            uint32_t lineOffset, PathId fileId)
       : m_parser(parser),
-        m_reportedSyntaxError(false),
+        m_reportedSyntaxError(0),
         m_watchDogOn(watchDogOn),
         m_barked(false),
         m_lineOffset(lineOffset),
@@ -70,7 +70,7 @@ class AntlrParserErrorListener : public antlr4::ANTLRErrorListener {
                                 antlr4::atn::ATNConfigSet *configs) override;
 
   ParseFile *m_parser;
-  bool m_reportedSyntaxError;
+  int m_reportedSyntaxError;
   bool m_watchDogOn;
   bool m_barked;
   uint32_t m_lineOffset;

diff --git a/src/SourceCompile/AntlrParserErrorListener.cpp b/src/SourceCompile/AntlrParserErrorListener.cpp
@@ -51,7 +51,7 @@ void AntlrParserErrorListener::syntaxError(
                 charPositionInLine, ":");
     }
   }
-  if (m_reportedSyntaxError == false) {
+  if (m_reportedSyntaxError < 10) {
     SymbolId msgId = m_parser->registerSymbol(msg);
     int32_t adjustedLine = m_parser->getLineNb(line + m_lineOffset);
     Location loc1(m_parser->getFileId(line + m_lineOffset), adjustedLine,
@@ -60,8 +60,8 @@ void AntlrParserErrorListener::syntaxError(
     Location loc3(m_parser->getCompileSourceFile()->getFileId(), 0, 0);
     Error err(ErrorDefinition::PA_SYNTAX_ERROR, {loc1, loc2, loc3});
     m_parser->addError(err);
-    m_reportedSyntaxError = true;
   }
+  m_reportedSyntaxError++;
 }
 
 void AntlrParserErrorListener::reportAmbiguity(

diff --git a/tests/PreProcMacro/PreProcMacro.log b/tests/PreProcMacro/PreProcMacro.log
@@ -219,10 +219,37 @@ AST_DEBUG_END
 [SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n    SURELOG_MACRO_NOT_DEFINED:check1!!!',
     SURELOG_MACRO_NOT_DEFINED:check1!!!  A 
     ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n    SURELOG_MACRO_NOT_DEFINED:check1!!!',
+    SURELOG_MACRO_NOT_DEFINED:check1!!!  A 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'A \n    "A is ifdef'd"',
+    "A is ifdef'd" 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:18:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"A is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
+    "A is not ifdef'd" 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:20:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n    SURELOG_MACRO_NOT_DEFINED:check1!!!',
+    SURELOG_MACRO_NOT_DEFINED:check1!!!  B 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n    SURELOG_MACRO_NOT_DEFINED:check1!!!',
+    SURELOG_MACRO_NOT_DEFINED:check1!!!  B 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'B \n    "B is ifdef'd"',
+    "B is ifdef'd" 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:27:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"B is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
+    "B is not ifdef'd" 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:29:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n    SURELOG_MACRO_NOT_DEFINED:check1!!!',
+    SURELOG_MACRO_NOT_DEFINED:check1!!!  A 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:.
+[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n    SURELOG_MACRO_NOT_DEFINED:check1!!!',
+    SURELOG_MACRO_NOT_DEFINED:check1!!!  A 
+    ^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:.
 [ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5: Unknown macro "check1".
 [ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:7: Unknown macro "check2".
 [  FATAL] : 0
-[ SYNTAX] : 1
+[ SYNTAX] : 10
 [  ERROR] : 4
 [WARNING] : 0
 [   NOTE] : 0
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -80,10 +80,10 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
 -- Configuring done (0.1s)
 -- Generating done (0.0s)
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[  6%] Generating 10_lsu_bus_intf.sv
+[  6%] Generating 12_beh_lib.sv
 [ 12%] Generating 13_ifu_mem_ctl.sv
-[ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 11_ifu_bp_ctl.sv
+[ 18%] Generating 11_ifu_bp_ctl.sv
+[ 25%] Generating 10_lsu_bus_intf.sv
 [ 31%] Generating 14_mem_lib.sv
 [ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
@@ -93,8 +93,8 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
 [ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
-[ 87%] Generating 8_ifu_aln_ctl.sv
-[ 93%] Generating 7_axi4_to_ahb.sv
+[ 87%] Generating 7_axi4_to_ahb.sv
+[ 93%] Generating 8_ifu_aln_ctl.sv
 [100%] Generating 9_tb_top.sv
 [100%] Built target Parse
 Surelog parsing status: 0