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tidy
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alaindargelas committed Sep 27, 2023
1 parent 3870020 commit 3318eb7
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Showing 3 changed files with 14 additions and 14 deletions.
2 changes: 1 addition & 1 deletion include/Surelog/Design/FileContent.h
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ class FileContent : public DesignComponent {
public:
FileContent(PathId fileId, Library* library, SymbolTable* symbolTable,
ErrorContainer* errors, FileContent* parent, PathId fileChunkId);
~FileContent();
~FileContent() override;

void setLibrary(Library* lib) { m_library = lib; }

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2 changes: 1 addition & 1 deletion src/SourceCompile/CompileSourceFile.cpp
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Expand Up @@ -134,7 +134,7 @@ CompileSourceFile::~CompileSourceFile() {
}
m_antlrPpMacroMap.clear();
m_antlrPpFileMap.clear();
if (m_fileAnalyzer) delete m_fileAnalyzer;
delete m_fileAnalyzer;
}

uint64_t CompileSourceFile::getJobSize(Action action) const {
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24 changes: 12 additions & 12 deletions third_party/tests/CoresSweRVMP/CoresSweRVMP.log
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Expand Up @@ -11,7 +11,7 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
CMake that the project does not need compatibility with older versions.


-- Configuring done (0.1s)
-- Configuring done (0.0s)
-- Generating done (0.0s)
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser
[100%] Generating preprocessing
Expand Down Expand Up @@ -134,21 +134,21 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
-- Configuring done (0.0s)
-- Generating done (0.0s)
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
[ 6%] Generating 10_lsu_bus_intf.sv
[ 12%] Generating 12_beh_lib.sv
[ 18%] Generating 11_ifu_bp_ctl.sv
[ 25%] Generating 13_ifu_mem_ctl.sv
[ 6%] Generating 16_dec_decode_ctl.sv
[ 12%] Generating 1_lsu_stbuf.sv
[ 31%] Generating 12_beh_lib.sv
[ 31%] Generating 14_mem_lib.sv
[ 37%] Generating 15_exu.sv
[ 43%] Generating 16_dec_decode_ctl.sv
[ 50%] Generating 1_lsu_stbuf.sv
[ 31%] Generating 13_ifu_mem_ctl.sv
[ 37%] Generating 11_ifu_bp_ctl.sv
[ 43%] Generating 15_exu.sv
[ 50%] Generating 10_lsu_bus_intf.sv
[ 56%] Generating 2_ahb_to_axi4.sv
[ 62%] Generating 3_rvjtag_tap.sv
[ 68%] Generating 4_dec_tlu_ctl.sv
[ 62%] Generating 4_dec_tlu_ctl.sv
[ 68%] Generating 3_rvjtag_tap.sv
[ 75%] Generating 5_lsu_bus_buffer.sv
[ 81%] Generating 6_dbg.sv
[ 87%] Generating 8_ifu_aln_ctl.sv
[ 93%] Generating 7_axi4_to_ahb.sv
[ 87%] Generating 7_axi4_to_ahb.sv
[ 93%] Generating 8_ifu_aln_ctl.sv
[100%] Generating 9_tb_top.sv
[100%] Built target Parse
Surelog parsing status: 0
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