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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,344 @@ | ||
| block/ADC: | ||
| description: Analog to digital converter. | ||
| items: | ||
| - name: STATR | ||
| description: status register. | ||
| byte_offset: 0 | ||
| fieldset: STATR | ||
| - name: CTLR1 | ||
| description: control register 1. | ||
| byte_offset: 4 | ||
| fieldset: CTLR1 | ||
| - name: CTLR2 | ||
| description: control register 2. | ||
| byte_offset: 8 | ||
| fieldset: CTLR2 | ||
| - name: SAMPTR1 | ||
| description: sample time register 1. | ||
| byte_offset: 12 | ||
| fieldset: SAMPTR1 | ||
| - name: SAMPTR2 | ||
| description: sample time register 2. | ||
| byte_offset: 16 | ||
| fieldset: SAMPTR2 | ||
| - name: IOFR | ||
| description: injected channel data offset register x. | ||
| array: | ||
| len: 4 | ||
| stride: 4 | ||
| byte_offset: 20 | ||
| fieldset: IOFR | ||
| - name: WDHTR | ||
| description: watchdog higher threshold register. | ||
| byte_offset: 36 | ||
| fieldset: WDHTR | ||
| - name: WDLTR | ||
| description: watchdog lower threshold register. | ||
| byte_offset: 40 | ||
| fieldset: WDLTR | ||
| - name: RSQR1 | ||
| description: regular sequence register 1. | ||
| byte_offset: 44 | ||
| fieldset: RSQR1 | ||
| - name: RSQR2 | ||
| description: regular sequence register 2. | ||
| byte_offset: 48 | ||
| fieldset: RSQR2 | ||
| - name: RSQR3 | ||
| description: regular sequence register 3. | ||
| byte_offset: 52 | ||
| fieldset: RSQR3 | ||
| - name: ISQR | ||
| description: injected sequence register. | ||
| byte_offset: 56 | ||
| fieldset: ISQR | ||
| - name: IDATAR | ||
| description: injected data register x. | ||
| array: | ||
| len: 4 | ||
| stride: 4 | ||
| byte_offset: 60 | ||
| access: Read | ||
| fieldset: IDATAR | ||
| - name: RDATAR | ||
| description: regular data register. | ||
| byte_offset: 76 | ||
| access: Read | ||
| fieldset: RDATAR | ||
| fieldset/CTLR1: | ||
| description: control register 1. | ||
| fields: | ||
| - name: AWDCH | ||
| description: Analog watchdog channel select bits. | ||
| bit_offset: 0 | ||
| bit_size: 5 | ||
| - name: EOCIE | ||
| description: Interrupt enable for EOC. | ||
| bit_offset: 5 | ||
| bit_size: 1 | ||
| - name: AWDIE | ||
| description: Analog watchdog interrupt enable. | ||
| bit_offset: 6 | ||
| bit_size: 1 | ||
| - name: JEOCIE | ||
| description: Interrupt enable for injected channels. | ||
| bit_offset: 7 | ||
| bit_size: 1 | ||
| - name: SCAN | ||
| description: Scan mode. | ||
| bit_offset: 8 | ||
| bit_size: 1 | ||
| - name: AWDSGL | ||
| description: Enable the watchdog on a single channel in scan mode. | ||
| bit_offset: 9 | ||
| bit_size: 1 | ||
| - name: JAUTO | ||
| description: Automatic injected group conversion. | ||
| bit_offset: 10 | ||
| bit_size: 1 | ||
| - name: DISCEN | ||
| description: Discontinuous mode on regular channels. | ||
| bit_offset: 11 | ||
| bit_size: 1 | ||
| - name: JDISCEN | ||
| description: Discontinuous mode on injected channels. | ||
| bit_offset: 12 | ||
| bit_size: 1 | ||
| - name: DISCNUM | ||
| description: Discontinuous mode channel count. | ||
| bit_offset: 13 | ||
| bit_size: 3 | ||
| - name: DUALMOD | ||
| description: Dual mode selection. | ||
| bit_offset: 16 | ||
| bit_size: 4 | ||
| - name: JAWDEN | ||
| description: Analog watchdog enable on injected channels. | ||
| bit_offset: 22 | ||
| bit_size: 1 | ||
| - name: AWDEN | ||
| description: Analog watchdog enable on regular channels. | ||
| bit_offset: 23 | ||
| bit_size: 1 | ||
| - name: TKENABLE | ||
| description: Touch key enable, including TKEY_F and TKEY_V. | ||
| bit_offset: 24 | ||
| bit_size: 1 | ||
| fieldset/CTLR2: | ||
| description: control register 2. | ||
| fields: | ||
| - name: ADON | ||
| description: A/D converter ON / OFF. | ||
| bit_offset: 0 | ||
| bit_size: 1 | ||
| - name: CONT | ||
| description: Continuous conversion. | ||
| bit_offset: 1 | ||
| bit_size: 1 | ||
| - name: CAL | ||
| description: A/D calibration. | ||
| bit_offset: 2 | ||
| bit_size: 1 | ||
| - name: RSTCAL | ||
| description: Reset calibration. | ||
| bit_offset: 3 | ||
| bit_size: 1 | ||
| - name: DMA | ||
| description: Direct memory access mode. | ||
| bit_offset: 8 | ||
| bit_size: 1 | ||
| - name: ALIGN | ||
| description: Data alignment. | ||
| bit_offset: 11 | ||
| bit_size: 1 | ||
| - name: JEXTSEL | ||
| description: External event select for injected group. | ||
| bit_offset: 12 | ||
| bit_size: 3 | ||
| - name: JEXTTRIG | ||
| description: External trigger conversion mode for injected channels. | ||
| bit_offset: 15 | ||
| bit_size: 1 | ||
| - name: EXTSEL | ||
| description: External event select for regular group. | ||
| bit_offset: 17 | ||
| bit_size: 3 | ||
| - name: EXTTRIG | ||
| description: External trigger conversion mode for regular channels. | ||
| bit_offset: 20 | ||
| bit_size: 1 | ||
| - name: JSWSTART | ||
| description: Start conversion of injected channels. | ||
| bit_offset: 21 | ||
| bit_size: 1 | ||
| - name: SWSTART | ||
| description: Start conversion of regular channels. | ||
| bit_offset: 22 | ||
| bit_size: 1 | ||
| - name: TSVREFE | ||
| description: Temperature sensor and VREFINT enable. | ||
| bit_offset: 23 | ||
| bit_size: 1 | ||
| fieldset/IDATAR: | ||
| description: injected data register x. | ||
| fields: | ||
| - name: JDATA | ||
| description: Injected data. | ||
| bit_offset: 0 | ||
| bit_size: 16 | ||
| fieldset/IOFR: | ||
| description: injected channel data offset register x. | ||
| fields: | ||
| - name: JOFFSET | ||
| description: Data offset for injected channel x. | ||
| bit_offset: 0 | ||
| bit_size: 12 | ||
| array: | ||
| len: 1 | ||
| stride: 0 | ||
| fieldset/ISQR: | ||
| description: injected sequence register. | ||
| fields: | ||
| - name: JSQ | ||
| description: 1st conversion in injected sequence. | ||
| bit_offset: 0 | ||
| bit_size: 5 | ||
| array: | ||
| len: 4 | ||
| stride: 5 | ||
| - name: JL | ||
| description: Injected sequence length. | ||
| bit_offset: 20 | ||
| bit_size: 2 | ||
| fieldset/RDATAR: | ||
| description: regular data register. | ||
| fields: | ||
| - name: DATA | ||
| description: Regular data. | ||
| bit_offset: 0 | ||
| bit_size: 16 | ||
| - name: ADC2DATA | ||
| description: ADC2 data. | ||
| bit_offset: 16 | ||
| bit_size: 16 | ||
| fieldset/RSQR1: | ||
| description: regular sequence register 1. | ||
| fields: | ||
| - name: SQ | ||
| description: 13th conversion in regular sequence. | ||
| bit_offset: 0 | ||
| bit_size: 5 | ||
| array: | ||
| len: 4 | ||
| stride: 5 | ||
| - name: L | ||
| description: Regular channel sequence length. | ||
| bit_offset: 20 | ||
| bit_size: 4 | ||
| fieldset/RSQR2: | ||
| description: regular sequence register 2. | ||
| fields: | ||
| - name: SQ | ||
| description: 7th conversion in regular sequence. | ||
| bit_offset: 0 | ||
| bit_size: 5 | ||
| array: | ||
| len: 6 | ||
| stride: 5 | ||
| fieldset/RSQR3: | ||
| description: regular sequence register 3. | ||
| fields: | ||
| - name: SQ | ||
| description: 1st conversion in regular sequence. | ||
| bit_offset: 0 | ||
| bit_size: 5 | ||
| array: | ||
| len: 6 | ||
| stride: 5 | ||
| fieldset/SAMPTR1: | ||
| description: sample time register 1. | ||
| fields: | ||
| - name: SMP | ||
| description: Channel 10 sample time selection. | ||
| bit_offset: 0 | ||
| bit_size: 3 | ||
| array: | ||
| len: 8 | ||
| stride: 3 | ||
| enum: SAMPLE_TIME | ||
| fieldset/SAMPTR2: | ||
| description: sample time register 2. | ||
| fields: | ||
| - name: SMP | ||
| description: Channel 0 sample time selection. | ||
| bit_offset: 0 | ||
| bit_size: 3 | ||
| array: | ||
| len: 10 | ||
| stride: 3 | ||
| enum: SAMPLE_TIME | ||
| fieldset/STATR: | ||
| description: status register. | ||
| fields: | ||
| - name: AWD | ||
| description: Analog watchdog flag. | ||
| bit_offset: 0 | ||
| bit_size: 1 | ||
| - name: EOC | ||
| description: Regular channel end of conversion. | ||
| bit_offset: 1 | ||
| bit_size: 1 | ||
| - name: JEOC | ||
| description: Injected channel end of conversion. | ||
| bit_offset: 2 | ||
| bit_size: 1 | ||
| - name: JSTRT | ||
| description: Injected channel start flag. | ||
| bit_offset: 3 | ||
| bit_size: 1 | ||
| - name: STRT | ||
| description: Regular channel start flag. | ||
| bit_offset: 4 | ||
| bit_size: 1 | ||
| fieldset/WDHTR: | ||
| description: watchdog higher threshold register. | ||
| fields: | ||
| - name: HT | ||
| description: Analog watchdog higher threshold. | ||
| bit_offset: 0 | ||
| bit_size: 12 | ||
| fieldset/WDLTR: | ||
| description: watchdog lower threshold register. | ||
| fields: | ||
| - name: LT | ||
| description: Analog watchdog lower threshold. | ||
| bit_offset: 0 | ||
| bit_size: 12 | ||
| enum/SAMPLE_TIME: | ||
| bit_size: 3 | ||
| description: Sample time selection | ||
| variants: | ||
| - name: Cycles1_5 | ||
| description: 1.5 cycles | ||
| value: 0 | ||
| - name: Cycles7_5 | ||
| description: 7.5 cycles | ||
| value: 1 | ||
| - name: Cycles13_5 | ||
| description: 13.5 cycles | ||
| value: 2 | ||
| - name: Cycles28_5 | ||
| description: 28.5 cycles | ||
| value: 3 | ||
| - name: Cycles41_5 | ||
| description: 41.5 cycles | ||
| value: 4 | ||
| - name: Cycles55_5 | ||
| description: 55.5 cycles | ||
| value: 5 | ||
| - name: Cycles71_5 | ||
| description: 71.5 cycles | ||
| value: 6 | ||
| - name: Cycles239_5 | ||
| description: 239.5 cycles | ||
| value: 7 |
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