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errors in row/cols on right
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bullwinkle3000 committed Dec 20, 2024
1 parent 07f9102 commit dc5bbf5
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Showing 6 changed files with 63 additions and 31 deletions.
33 changes: 19 additions & 14 deletions .idea/workspace.xml

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6 changes: 3 additions & 3 deletions config/boards/pillbug.overlay
Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,9 @@



&blackpill_i2c {
status = "disabled";
};
//&blackpill_i2c {
// status = "disabled";
//};

&blackpill_serial {
status = "disabled";
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27 changes: 27 additions & 0 deletions config/boards/shields/wyld_dm/Kconfig.defconfig
Original file line number Diff line number Diff line change
Expand Up @@ -13,4 +13,31 @@ if SHIELD_WYLD_DM_LEFT || SHIELD_WYLD_DM_RIGHT
config ZMK_SPLIT
default y

if ZMK_DISPLAY

config I2C
default y

config SSD1306
default y

endif # ZMK_DISPLAY

if LVGL

config LV_Z_VDB_SIZE
default 64

config LV_DPI_DEF
default 148

config LV_Z_BITS_PER_PIXEL
default 1

choice LV_COLOR_DEPTH
default LV_COLOR_DEPTH_1
endchoice

endif # LVGL

endif
8 changes: 4 additions & 4 deletions config/boards/shields/wyld_dm/wyld_dm.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -56,10 +56,10 @@

RC(1,0) RC(1,1) RC(1,2) RC(1,3) RC(1,4) RC(1,5) RC(1,6) RC(1,7) RC(1,8) RC(1,9) RC(1,10) RC(1,11) RC(1,12) RC(1,13)
RC(2,0) RC(2,1) RC(2,2) RC(2,3) RC(2,4) RC(2,5) RC(2,6) RC(2,7) RC(2,8) RC(2,9) RC(2,10) RC(2,11) RC(2,12) RC(2,13)
RC(3,0) RC(3,1) RC(3,2) RC(0,3) RC(3,4) RC(3,5) RC(3,6) RC(3,7) RC(3,8) RC(3,9) RC(3,10) RC(3,11) RC(3,12) RC(3,13)
RC(4,0) RC(4,1) RC(4,2) RC(0,3) RC(4,4) RC(4,5) RC(4,6) RC(6,5) RC(6,7) RC(4,7) RC(4,8) RC(4,9) RC(4,10) RC(4,11) RC(4,12) RC(4,13)
RC(5,0) RC(5,1) RC(5,2) RC(0,3) RC(5,4) RC(4,5) RC(5,6) RC(5,7) RC(5,8) RC(5,9) RC(5,10) RC(5,11) RC(5,12) RC(5,13)
RC(6,0) RC(6,1) RC(6,2) RC(4,3) RC(6,4) RC(6,9) RC(6,10) RC(6,11) RC(6,12) RC(6,13)
RC(3,0) RC(3,1) RC(3,2) RC(3,3) RC(3,4) RC(3,5) RC(3,6) RC(3,7) RC(3,8) RC(3,9) RC(3,10) RC(3,11) RC(3,12) RC(3,13)
RC(4,0) RC(4,1) RC(4,2) RC(4,3) RC(4,4) RC(4,5) RC(4,6) RC(6,5) RC(6,7) RC(4,7) RC(4,8) RC(4,9) RC(4,10) RC(4,11) RC(4,12) RC(4,13)
RC(5,0) RC(5,1) RC(5,2) RC(5,3) RC(5,4) RC(5,5) RC(5,6) RC(5,7) RC(5,8) RC(5,9) RC(5,10) RC(5,11) RC(5,12) RC(5,13)
RC(6,0) RC(6,1) RC(6,2) RC(6,3) RC(6,4) RC(6,9) RC(6,10) RC(6,11) RC(6,12) RC(6,13)
RC(0,0) RC(0,1) RC(0,2) RC(0,9) RC(0,8) RC(0,7)
RC(0,3) RC(0,4) RC(0,5) RC(0,12) RC(0,11) RC(0,10)
>;
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18 changes: 9 additions & 9 deletions config/wyld_dm.conf
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ CONFIG_ZMK_KSCAN_MATRIX_WAIT_BETWEEN_OUTPUTS=5

CONFIG_PINCTRL=y
CONFIG_GPIO=y
# CONFIG_I2C=y
CONFIG_I2C=y
CONFIG_SPI=y

#enable deep sleep
Expand Down Expand Up @@ -61,11 +61,11 @@ CONFIG_EC11=y
CONFIG_EC11_TRIGGER_GLOBAL_THREAD=y

#enable displays
# CONFIG_ZMK_DISPLAY=y
# CONFIG_I2C=y
# CONFIG_SSD1306=y
# CONFIG_ZMK_DISPLAY_STATUS_SCREEN_BUILT_IN=y
# CONFIG_ZMK_WIDGET_LAYER_STATUS=y
# CONFIG_ZMK_WIDGET_BATTERY_STATUS_SHOW_PERCENTAGE=y
# CONFIG_ZMK_DISPLAY_WORK_QUEUE_SYSTEM=y
# CONFIG_ZMK_DISPLAY_INVERT=y
CONFIG_ZMK_DISPLAY=y
CONFIG_I2C=y
CONFIG_SSD1306=y
CONFIG_ZMK_DISPLAY_STATUS_SCREEN_BUILT_IN=y
CONFIG_ZMK_WIDGET_LAYER_STATUS=y
CONFIG_ZMK_WIDGET_BATTERY_STATUS_SHOW_PERCENTAGE=y
CONFIG_ZMK_DISPLAY_WORK_QUEUE_SYSTEM=y
CONFIG_ZMK_DISPLAY_INVERT=y
2 changes: 1 addition & 1 deletion config/wyld_dm.keymap
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@
&trans &ext_power EP_ON &ext_power EP_OFF &ext_power EP_TOG &bootloader &trans &trans &trans &kp MINUS &kp KP_PLUS &kp LBRC &kp RBRC &kp PIPE &trans
&trans &rgb_ug RGB_ON &rgb_ug RGB_OFF &rgb_ug RGB_EFF &rgb_ug RGB_EFR &trans &trans &rgb_ug RGB_TOG &trans &trans &trans &trans &trans &trans &trans &trans
&trans &trans &trans &trans &trans &trans &trans &trans &trans &trans &trans &trans &trans &trans
&bootloader &trans &trans &trans &trans &trans &trans &trans &trans &bootloader
&bootloader &trans &trans &trans &trans &trans &trans &trans &trans &bootloader
&trans &trans &trans &trans &trans &trans
&trans &trans &trans &trans &trans &trans

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