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REWORKED ROWS
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bullwinkle3000 committed Dec 21, 2024
1 parent 03b3319 commit 73feeee
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22 changes: 11 additions & 11 deletions .idea/workspace.xml

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16 changes: 8 additions & 8 deletions config/boards/shields/wyld_dm/wyld_dm.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -54,14 +54,14 @@
// 6x7 with encoders
map = <

RC(1,0) RC(1,1) RC(1,2) RC(1,3) RC(1,4) RC(1,5) RC(1,6) RC(1,7) RC(1,8) RC(1,9) RC(1,10) RC(1,11) RC(1,12) RC(1,13)
RC(2,0) RC(2,1) RC(2,2) RC(2,3) RC(2,4) RC(2,5) RC(2,6) RC(2,7) RC(2,8) RC(2,9) RC(2,10) RC(2,11) RC(2,12) RC(2,13)
RC(3,0) RC(3,1) RC(3,2) RC(3,3) RC(3,4) RC(3,5) RC(3,6) RC(3,7) RC(3,8) RC(3,9) RC(3,10) RC(3,11) RC(3,12) RC(3,13)
RC(4,0) RC(4,1) RC(4,2) RC(4,3) RC(4,4) RC(4,5) RC(4,6) RC(6,5) RC(6,7) RC(4,7) RC(4,8) RC(4,9) RC(4,10) RC(4,11) RC(4,12) RC(4,13)
RC(5,0) RC(5,1) RC(5,2) RC(5,3) RC(5,4) RC(5,5) RC(5,6) RC(5,7) RC(5,8) RC(5,9) RC(5,10) RC(5,11) RC(5,12) RC(5,13)
RC(6,0) RC(6,1) RC(6,2) RC(6,3) RC(6,4) RC(6,9) RC(6,10) RC(6,11) RC(6,12) RC(6,13)
RC(0,0) RC(0,1) RC(0,2) RC(0,9) RC(0,8) RC(0,7)
RC(0,3) RC(0,4) RC(0,5) RC(0,12) RC(0,11) RC(0,10)
RC(0,0) RC(0,1) RC(0,2) RC(0,3) RC(0,4) RC(0,5) RC(0,6) RC(0,7) RC(0,8) RC(0,9) RC(0,10) RC(0,11) RC(0,12) RC(0,13)
RC(1,0) RC(1,1) RC(1,2) RC(1,3) RC(1,4) RC(1,5) RC(1,6) RC(1,7) RC(1,8) RC(1,9) RC(1,10) RC(1,11) RC(1,12) RC(1,13)
RC(2,0) RC(2,1) RC(2,2) RC(2,3) RC(2,4) RC(2,5) RC(2,6) RC(2,7) RC(2,8) RC(2,9) RC(2,10) RC(2,11) RC(2,12) RC(2,13)
RC(3,0) RC(3,1) RC(3,2) RC(3,3) RC(3,4) RC(3,5) RC(3,6) RC(5,5) RC(5,7) RC(3,7) RC(3,8) RC(3,9) RC(3,10) RC(3,11) RC(3,12) RC(3,13)
RC(4,0) RC(4,1) RC(4,2) RC(4,3) RC(4,4) RC(4,5) RC(4,6) RC(4,7) RC(4,8) RC(4,9) RC(4,10) RC(4,11) RC(4,12) RC(4,13)
RC(5,0) RC(5,1) RC(5,2) RC(5,3) RC(5,4) RC(5,9) RC(5,10) RC(5,11) RC(5,12) RC(5,13)
RC(6,0) RC(6,1) RC(6,2) RC(6,9) RC(6,8) RC(6,7)
RC(6,3) RC(6,4) RC(6,5) RC(6,12) RC(6,11) RC(6,10)
>;

// map = <
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