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riscv : fix the inverted logc interrupt-are-disabled-while-single-ste… #1767

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merged 1 commit into from
Nov 21, 2024
Merged

riscv : fix the inverted logc interrupt-are-disabled-while-single-ste… #1767

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6 changes: 4 additions & 2 deletions src/target/riscv_debug.c
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Original file line number Diff line number Diff line change
Expand Up @@ -132,6 +132,8 @@
#define RV_DCSR_CAUSE_MASK 0x000001c0U
#define RV_DCSR_STEPIE 0x00000800U
#define RV_DCSR_EBREAK_MACHINE 0x00008000U
#define RV_DCSR_STOP_TIME (1U << 9)
#define RV_DCSR_STOP_COUNT (1U << 10)

#define RV_GPRS_COUNT 32U

Expand Down Expand Up @@ -1014,9 +1016,9 @@ static void riscv_halt_resume(target_s *target, const bool step)
if (!riscv_csr_read(hart, RV_DCSR | RV_CSR_FORCE_32_BIT, &stepping_config))
return;
if (step)
stepping_config |= RV_DCSR_STEP | RV_DCSR_STEPIE;
stepping_config |= RV_DCSR_STEP | RV_DCSR_STOP_TIME | RV_DCSR_STOP_COUNT;
else {
stepping_config &= ~(RV_DCSR_STEP | RV_DCSR_STEPIE);
stepping_config &= ~(RV_DCSR_STEP);
stepping_config |= RV_DCSR_EBREAK_MACHINE;
}
if (!riscv_csr_write(hart, RV_DCSR | RV_CSR_FORCE_32_BIT, &stepping_config))
Expand Down
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