Add driver for SwCc after rebase.

.github/synthesis/debug.json

@@ -0,0 +1,3 @@
+[
+  {"top": "swCcTopologyTest",              "stage": "test"}
+]

bittide-experiments/src/Bittide/Plot.hs

@@ -41,7 +41,7 @@ import Graphics.Matplotlib (
 import Graphics.Matplotlib qualified as MP (plot)
 
 import Bittide.ClockControl (RelDataCount)
-import Bittide.ClockControl.Callisto (ReframingState (..))
+import Bittide.ClockControl.Callisto.Types (ReframingState (..))
 import Bittide.ClockControl.StabilityChecker qualified as SC (StabilityIndication (..))
 import Bittide.Topology
 

bittide-instances/bittide-instances.cabal

@@ -92,6 +92,7 @@ common common-options
     clash-prelude,
     clash-protocols,
     clash-vexriscv,
+    clock,
     constraints >=0.13.3 && <0.15,
     containers,
     cryptohash-sha256,
@@ -132,6 +133,7 @@ library
     Bittide.Instances.Hitl.BoardTest
     Bittide.Instances.Hitl.DnaOverSerial
     Bittide.Instances.Hitl.Driver.DnaOverSerial
+    Bittide.Instances.Hitl.Driver.SwCcTopologies
     Bittide.Instances.Hitl.Driver.VexRiscv
     Bittide.Instances.Hitl.Driver.VexRiscvTcp
     Bittide.Instances.Hitl.Ethernet
@@ -151,7 +153,6 @@ library
     Bittide.Instances.Hitl.Utils.Vivado
     Bittide.Instances.Hitl.VexRiscv
     Bittide.Instances.Pnr.Calendar
-    Bittide.Instances.Pnr.ClockControl
     Bittide.Instances.Pnr.Counter
     Bittide.Instances.Pnr.ElasticBuffer
     Bittide.Instances.Pnr.Ethernet

bittide-instances/data/constraints/jtag_pmod1-alt.xdc

@@ -0,0 +1,16 @@
+# SPDX-FileCopyrightText: 2024 Google LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# PMOD1_[0..7]
+# Note that there are no clock capable pins in this list
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AP16} [get_ports {JTAG_TCK}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AP15} [get_ports {JTAG_TDI}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM16} [get_ports {JTAG_RST}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM15} [get_ports {JTAG_TMS}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN18} [get_ports {JTAG_TDO}]
+
+# PMOD1 does not have a clock capable pin. To Vivado's credit, it refuses to
+# produce a bitstream if we try to use a non-clock capable pin as a clock. With
+# the following line, we tell Vivado to ignore this warning.
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTAG_TCK]

bittide-instances/data/constraints/swCcTopologyTest.xdc

@@ -0,0 +1,44 @@
+# SPDX-FileCopyrightText: 2024 Google LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set_property BOARD_PART_PIN sysclk_125_n [get_ports SYSCLK_125_n]
+set_property BOARD_PART_PIN sysclk_125_p [get_ports SYSCLK_125_p]
+set_property BOARD_PART_PIN sma_mgt_refclk_n [get_ports SMA_MGT_REFCLK_C_n]
+set_property BOARD_PART_PIN sma_mgt_refclk_p [get_ports SMA_MGT_REFCLK_C_p]
+
+set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports spiDone]
+
+set_clock_groups \
+  -asynchronous \
+  -group [get_clocks -include_generated_clocks {SYSCLK_125_p}] \
+  -group [get_clocks -include_generated_clocks {SMA_MGT_REFCLK_C_p}]
+
+# Color   | FPGA pin      | LVLSHFT       | Connection
+# --------|---------------|---------------|------------------
+# Grey    | PMOD0_0       | IO1           | SYNC_OUT (legacy)
+# Blue    | PMOD0_1       | IO2           | FINC
+# Yellow  | PMOD0_2       | IO3           | MOSI/SDIO
+# Red     | PMOD0_3       | IO4           | SCLK
+# White   | PMOD0_4       | IO5           | SYNC_IN (legacy)
+# Purple  | PMOD0_5       | IO6           | FDEC
+# Green   | PMOD0_6       | IO7           | CSB
+# Orange  | PMOD0_7       | IO8           | MISO/SDO
+# Black   | Not connected | Not connected |
+# Brown   | PMOD_GND      | GND           | GND (SPI)
+
+# PMOD1_[0..7]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN21} [get_ports {FINC}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AH18} [get_ports {MOSI}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {SCLK}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AF25} [get_ports {FDEC}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE21} [get_ports {CSB}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM17} [get_ports {MISO}]
+
+# PMOD0_3
+# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {shared_reset_btn}]
+
+# USER SMA GPIO_P
+set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN H27} [get_ports {SYNC_IN}]
+# USER_SMA_GPIO_N (connected on node 0 to SYNC_IN of all nodes)
+set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN G27} [get_ports {SYNC_OUT}]

bittide-instances/data/openocd/ports.tcl

@@ -7,7 +7,17 @@ if { $user_gdb_port == "" } {
   error "Required environment variable 'GDB_PORT' is not set."
 }
 
+set user_tcl_port [env TCL_PORT]
+if { $user_tcl_port == "" } {
+  error "Required environment variable 'TCL_PORT' is not set."
+}
+
+set user_telnet_port [env TELNET_PORT]
+if { $user_telnet_port == "" } {
+  error "Required environment variable 'TELNET_PORT' is not set."
+}
+
 bindto 0.0.0.0
 gdb_port $user_gdb_port
-tcl_port 6666
-telnet_port 4444
+tcl_port $user_tcl_port
+telnet_port $user_telnet_port

bittide-instances/data/openocd/start.sh

@@ -2,5 +2,21 @@
 # SPDX-FileCopyrightText: 2024 Google LLC
 #
 # SPDX-License-Identifier: Apache-2.0
+set -e
+
+# Default stdout to /dev/null
+OPENOCD_STDOUT_LOG="${OPENOCD_STDOUT_LOG:-/dev/null}"
+stdout_dir=$(dirname "${OPENOCD_STDOUT_LOG}")
+mkdir -p "${stdout_dir}"
+OPENOCD_STDOUT_LOG="$(realpath ${OPENOCD_STDOUT_LOG})"
+
+# Default stderr to /dev/null
+OPENOCD_STDERR_LOG="${OPENOCD_STDERR_LOG:-/dev/null}"
+stderr_dir=$(dirname "${OPENOCD_STDERR_LOG}")
+mkdir -p "${stderr_dir}"
+OPENOCD_STDERR_LOG="$(realpath ${OPENOCD_STDERR_LOG})"
+
 cd $(dirname $0)
-exec openocd-vexriscv -f ports.tcl -f sipeed.tcl -f vexriscv_init.tcl $@
+openocd-vexriscv -f ports.tcl -f sipeed.tcl -f vexriscv_init.tcl $@ \
+  > >(tee "${OPENOCD_STDOUT_LOG}") \
+  2> >(tee "${OPENOCD_STDERR_LOG}" >&2)