Bump clash-protocols

See:

  clash-lang/clash-protocols#67
  clash-lang/clash-protocols#68
  clash-lang/clash-protocols#69

bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs

@@ -73,7 +73,6 @@ import Clash.Xilinx.ClockGen
 
 import Protocols
 import Protocols.Wishbone
-import Protocols.Internal
 
 type NodeCount = 8 :: Nat
 
@@ -95,9 +94,6 @@ c_CLOCK_PATHS =
 -- domain encodes them as related.
 type TransceiverWires dom = Vec 7 (Signal dom (BitVector 1))
 
-unitCS :: CSignal dom ()
-unitCS = CSignal (pure ())
-
 -- | Instantiates a RiscV core that copies instructions coming from a hardware
 -- implementation of Callisto (see 'fullMeshHwTest') and copies it to a register
 -- tied to FINC/FDEC.
@@ -114,14 +110,14 @@ fullMeshRiscvCopyTest ::
   )
 fullMeshRiscvCopyTest clk rst callistoResult dataCounts = unbundle fIncDec
  where
-  (_, CSignal fIncDec) = toSignals
+  (_, fIncDec) = toSignals
     ( circuit $ \unit -> do
       [wbA, wbB] <- withClockResetEnable clk rst enableGen $ processingElement @dom peConfig -< unit
       fIncDecCallisto -< wbA
       (fIncDec, _allStable) <- withClockResetEnable clk rst enableGen $
         clockControlWb margin framesize (pure $ complement 0) dataCounts -< wbB
       idC -< fIncDec
-    ) ((), unitCS)
+    ) ((), pure ())
 
   fIncDecCallisto ::
     forall aw nBytes .

bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs

@@ -68,7 +68,6 @@ import Clash.Sized.Extra (unsignedToSigned)
 import Clash.Xilinx.ClockGen
 
 import Protocols
-import Protocols.Internal
 
 type NodeCount = 8 :: Nat
 
@@ -90,9 +89,6 @@ c_CLOCK_PATHS =
 -- domain encodes them as related.
 type TransceiverWires dom = Vec 7 (Signal dom (BitVector 1))
 
-unitCS :: CSignal dom ()
-unitCS = CSignal (pure ())
-
 -- | Instantiates a RiscV core
 fullMeshRiscvTest ::
   forall dom .
@@ -106,13 +102,13 @@ fullMeshRiscvTest ::
   )
 fullMeshRiscvTest clk rst dataCounts = unbundle fIncDec
  where
-  (_, CSignal fIncDec) = toSignals
+  (_, fIncDec) = toSignals
     ( circuit $ \unit -> do
       [wbB] <- withClockResetEnable clk rst enableGen $ processingElement @dom peConfig -< unit
       (fIncDec, _allStable) <- withClockResetEnable clk rst enableGen $
         clockControlWb margin framesize (pure $ complement 0) dataCounts -< wbB
       idC -< fIncDec
-    ) ((), unitCS)
+    ) ((), pure ())
 
   margin = d2
 

bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs

@@ -15,7 +15,6 @@ import Clash.Explicit.Prelude (noReset, orReset)
 import Clash.Xilinx.ClockGen (clockWizardDifferential)
 import Language.Haskell.TH (runIO)
 import Protocols
-import Protocols.Internal
 import Protocols.Wishbone
 import System.FilePath
 
@@ -41,17 +40,16 @@ vexRiscvInner = stateToDoneSuccess <$> status
     stateToDoneSuccess Success = (True, True)
     stateToDoneSuccess Fail    = (True, False)
 
-    unitC = CSignal (pure ())
-    (_, CSignal status) = circuitFn ((), unitC)
+    (_, status) = circuitFn ((), pure ())
 
     Circuit circuitFn = circuit $ \unit -> do
         [wb] <- processingElement peConfig -< unit
         statusRegister -< wb
 
     statusRegister :: Circuit (Wishbone dom 'Standard 30 (Bytes 4)) (CSignal dom TestStatus)
-    statusRegister = Circuit $ \(fwd, CSignal _) ->
+    statusRegister = Circuit $ \(fwd, _) ->
         let (unbundle -> (m2s, st)) = mealy go Running fwd
-        in (m2s, CSignal st)
+        in (m2s, st)
       where
         go st WishboneM2S{..}
           -- out of cycle, no response, same state

bittide-instances/src/Bittide/Instances/Pnr/ProcessingElement.hs

@@ -12,7 +12,6 @@ import Clash.Explicit.Prelude(orReset, noReset)
 import Clash.Xilinx.ClockGen
 import Language.Haskell.TH
 import Protocols
-import Protocols.Internal
 import System.FilePath
 
 import Bittide.DoubleBufferedRam
@@ -28,8 +27,8 @@ import Project.FilePath
 vexRiscUartHello ::
   "SYSCLK_300" ::: DiffClock Ext300 ->
   "CPU_RESET" ::: Reset Basic200 ->
-  ("USB_UART_TX" ::: CSignal Basic200 Bit, CSignal Basic200 ()) ->
-  (CSignal Basic200 (), "USB_UART_RX" ::: CSignal Basic200 Bit)
+  ("USB_UART_TX" ::: Signal Basic200 Bit, Signal Basic200 ()) ->
+  (Signal Basic200 (), "USB_UART_RX" ::: Signal Basic200 Bit)
 vexRiscUartHello diffClk rst_in =
   toSignals $ withClockResetEnable clk200 rst200 enableGen $
     circuit $ \uartRx -> do

bittide-instances/tests/Wishbone/Time.hs

@@ -24,7 +24,6 @@ import Data.Maybe
 import Language.Haskell.TH
 import Project.FilePath
 import Protocols
-import Protocols.Internal(CSignal(..))
 import System.FilePath
 import Test.Tasty
 import Test.Tasty.HUnit
@@ -51,7 +50,7 @@ case_time_rust_self_test =
   ena = enableGen
   simResult = fmap (asciiToChar . fromIntegral) $ catMaybes $ sampleN 1_000_000 uartStream
   (uartStream, _, _) = withClockResetEnable (clockGen @Basic50) rst ena $ uart baud uartTx (pure Nothing)
-  (_, CSignal uartTx) = dut baud (clockToDiffClock clk) rst (CSignal $ pure 0, CSignal $ pure ())
+  (_, uartTx) = dut baud (clockToDiffClock clk) rst (pure 0, pure ())
 
 -- | A simple instance containing just VexRisc and UART as peripheral.
 -- Runs the `hello` binary from `firmware-binaries`.
@@ -61,8 +60,8 @@ dut ::
   SNat baud ->
   "SYSCLK_300" ::: DiffClock Ext300 ->
   "CPU_RESET" ::: Reset dom ->
-  ("USB_UART_TX" ::: CSignal dom Bit, CSignal dom ()) ->
-  (CSignal dom (), "USB_UART_RX" ::: CSignal dom Bit)
+  ("USB_UART_TX" ::: Signal dom Bit, Signal dom ()) ->
+  (Signal dom (), "USB_UART_RX" ::: Signal dom Bit)
 dut baud diffClk rst_in =
   toSignals $ withClockResetEnable clk200 rst200 enableGen $
     circuit $ \uartRx -> do

bittide/src/Bittide/ClockControl/Registers.hs

@@ -1,4 +1,4 @@
--- SPDX-FileCopyrightText: 2023 Google LLC
+-- SPDX-FileCopyrightText: 2023-2024 Google LLC
 --
 -- SPDX-License-Identifier: Apache-2.0
 
@@ -11,7 +11,6 @@ module Bittide.ClockControl.Registers where
 import Clash.Prelude
 
 import Protocols
-import Protocols.Internal
 import Protocols.Wishbone
 
 import Bittide.ClockControl
@@ -66,7 +65,7 @@ clockControlWb ::
     (CSignal dom ("FINC" ::: Bool, "FDEC" ::: Bool), CSignal dom ("ALL_STABLE" ::: Bool))
 clockControlWb margin framesize linkMask counters = Circuit go
  where
-  go (wbM2S, _) = (wbS2M, (CSignal fIncDec3, CSignal (all (==True) <$> (fmap stable <$> stabilityIndications))))
+  go (wbM2S, _) = (wbS2M, (fIncDec3, all (==True) <$> (fmap stable <$> stabilityIndications)))
    where
     stabilityIndications = bundle $ stabilityChecker margin framesize <$> counters
     readVec = dflipflop <$> (

bittide/src/Bittide/Wishbone.hs

@@ -24,7 +24,6 @@ import Data.Constraint.Nat.Extra
 import Data.Maybe
 
 import Protocols
-import Protocols.Internal(CSignal(..))
 import Protocols.Wishbone
 
 import qualified Protocols.Df as Df
@@ -89,11 +88,8 @@ dupWb ::
     )
 dupWb = Circuit go
   where
-    go (m2s0, (s2m0, (CSignal _, CSignal _))) =
-      (s2m0, (m2s0, (CSignal m2s0, CSignal s2m0)))
-
-unitCS :: CSignal dom ()
-unitCS = CSignal (pure ())
+    go (m2s0, (s2m0, _)) =
+      (s2m0, (m2s0, (m2s0, s2m0)))
 
 -- | An ILA monitoring all M2S and S2M signals on a Wishbone bus. Installs two
 -- extra signals 'capture' and 'trigger' that can be used as defaults for triggering
@@ -209,7 +205,7 @@ singleMasterInterconnect' config master slaves = (toMaster, bundle toSlaves)
 -- This function is unsafe because data can be lost when the input is @Just _@ and
 -- the receiving circuit tries to apply back pressure.
 unsafeToDf :: Circuit (CSignal dom (Maybe a)) (Df dom a)
-unsafeToDf = Circuit $ \ (CSignal cSig, _) -> (CSignal $ pure (), Df.maybeToData <$> cSig)
+unsafeToDf = Circuit $ \ (cSig, _) -> (pure (), Df.maybeToData <$> cSig)
 
 -- | 'Df' version of 'uart'.
 uartDf ::
@@ -226,9 +222,9 @@ uartDf ::
     )
 uartDf baud = Circuit go
  where
-  go ((request, ~(CSignal rxBit)),_) =
-    ( (Ack <$> ack, CSignal $ pure ())
-    , (CSignal received, CSignal txBit) )
+  go ((request, rxBit),_) =
+    ( (Ack <$> ack, pure ())
+    , (received, txBit) )
    where
     (received, txBit, ack) = uart baud rxBit (Df.dataToMaybe <$> request)
 
@@ -281,14 +277,12 @@ uartWb txDepth@SNat rxDepth@SNat baud = circuit $ \(wb, uartRx) -> do
       , CSignal dom (Bool, Bool) -- (rxEmpty, txFull)
       )
   wbToDf = Circuit $
-    bimap (third CSignal . unbundle) (second CSignal . unbundle) .
+    bimap unbundle unbundle .
     unbundle .
     fmap go .
     bundle .
-    bimap (bundle . third unCSignal) (bundle . second unCSignal)
+    bimap bundle bundle
    where
-    third f (a, b, c) = (a, b, f c)
-    unCSignal (CSignal s) = s
     go ((WishboneM2S{..}, Df.dataToMaybe -> rxData, fifoFull -> txFull), (Ack txAck, _))
       -- not in cycle
       | not (busCycle && strobe)
@@ -361,7 +355,7 @@ fifoWithMeta ::
   Circuit (Df dom a) (Df dom a, CSignal dom (FifoMeta depth))
 fifoWithMeta depth@SNat = Circuit circuitFunction
  where
-  circuitFunction (fifoIn, (readyIn, _)) = (Ack <$> readyOut, (fifoOut, CSignal fifoMeta))
+  circuitFunction (fifoIn, (readyIn, _)) = (Ack <$> readyOut, (fifoOut, fifoMeta))
    where
     circuitActive = unsafeToActiveLow hasReset .&&. fromEnable hasEnable
     bramOut =

bittide/src/Clash/Cores/UART/Extra.hs

@@ -1,4 +1,4 @@
--- SPDX-FileCopyrightText: 2023 Google LLC
+-- SPDX-FileCopyrightText: 2023-2024 Google LLC
 --
 -- SPDX-License-Identifier: Apache-2.0
 
@@ -18,7 +18,6 @@ import Data.Maybe
 import GHC.IO
 import Protocols
 import Protocols.Df hiding (catMaybes, sample, pure)
-import Protocols.Internal
 import System.IO
 
 import Bittide.Wishbone

cabal.project

@@ -96,7 +96,7 @@ source-repository-package
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-protocols.git
-  tag: eb76cd1be746ae91beff60c0f16d8c1dd888662c
+  tag: 7a451a7d6786ac450f23f022b7055fe61b70d3b2
 
 source-repository-package
   type: git