Remove unused uartRx from simulation tests

bittide · Dec 13, 2024 · 0bc27c9 · 0bc27c9
1 parent a828bcb
commit 0bc27c9
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Showing 2 changed files with 8 additions and 9 deletions.
diff --git a/bittide-instances/tests/Wishbone/CaptureUgn.hs b/bittide-instances/tests/Wishbone/CaptureUgn.hs
@@ -66,7 +66,6 @@ case_capture_ugn_self_test =
     sampleC def
       $ withClockResetEnable clk rst enableGen
       $ dut @System eb localCounter
-      <| idleSource
 
   {- The local counter starts counting up from 0x1122334411223344. The elastic buffer
   outputs Nothing for 1000 cycles, after which it will  start outputting a decreasing
@@ -89,10 +88,10 @@ dut ::
   Signal dom (Maybe (BitVector 64)) ->
   -- | Local sequence counter
   Signal dom (Unsigned 64) ->
-  Circuit (Df dom (BitVector 8)) (Df dom (BitVector 8))
-dut eb localCounter = circuit $ \uartRx -> do
+  Circuit () (Df dom (BitVector 8))
+dut eb localCounter = circuit $ do
   eb <- ebCircuit -< ()
-  jtagIdle <- idleSource -< ()
+  (uartRx, jtagIdle) <- idleSource -< ()
   [uartBus, ugnBus] <- processingElement @dom NoDumpVcd peConfig -< jtagIdle
   (uartTx, _uartStatus) <- uartInterfaceWb d2 d2 uartSim -< (uartBus, uartRx)
   _bittideData <- captureUgn localCounter -< (ugnBus, eb)

diff --git a/bittide-instances/tests/Wishbone/DnaPortE2.hs b/bittide-instances/tests/Wishbone/DnaPortE2.hs
@@ -46,18 +46,18 @@ case_dna_port_self_test = assertBool msg (receivedDna == simDna2)
   clk = clockGen
   rst = resetGen
   simResult = chr . fromIntegral <$> mapMaybe Df.dataToMaybe uartStream
-  uartStream = sampleC def $ withClockResetEnable clk rst enableGen $ dut @System <| idleSource
+  uartStream = sampleC def $ withClockResetEnable clk rst enableGen $ dut @System
 
 {- | A simple instance containing just VexRisc with UART and the DNA peripheral which
 runs the `dna_port_e2_test` binary from `firmware-binaries`.
 -}
 dut ::
   forall dom.
   (HiddenClockResetEnable dom) =>
-  Circuit (Df dom (BitVector 8)) (Df dom (BitVector 8))
-dut = circuit $ \uartRx -> do
-  jtag <- idleSource -< ()
-  [uartBus, dnaWb] <- processingElement @dom NoDumpVcd peConfig -< jtag
+  Circuit () (Df dom (BitVector 8))
+dut = circuit $ do
+  (uartRx, jtagIdle) <- idleSource -< ()
+  [uartBus, dnaWb] <- processingElement @dom NoDumpVcd peConfig -< jtagIdle
   (uartTx, _uartStatus) <- uartInterfaceWb d2 d2 uartSim -< (uartBus, uartRx)
   readDnaPortE2Wb simDna2 -< dnaWb
   idC -< uartTx