CI

Change to be hidden clock, reset, and enable. #6542

Sign in to view logs

Triggered via push December 16, 2024 12:32

rslawson

rs/swCcTopologiesTest

Status Success

Total duration 43m 30s

Artifacts 11

ci.yml

on: push

Build dependencies

bittide-instances hardware-in-the-loop test matrix generation

bittide-instances synthesis matrix generation

bittide-experiments unittests

Firmware Support Unit Tests

Firmware Limit Checks

bittide-instances doctests

bittide-instances unittests

Matrix: synth

Matrix: HITL

Generate clock control report

All jobs finished

Annotations

3 warnings

synth (transceiversUpTest, test)

Delete stale container networks failed, docker network prune fail with exit code 1

HITL (linkConfigurationTest, test)

No files were found with the provided path: _build/vivado/*/ila-data _build/hitl/*. No artifacts will be uploaded.

HITL (transceiversUpTest, test)

No files were found with the provided path: _build/vivado/*/ila-data _build/hitl/*. No artifacts will be uploaded.

Artifacts

Produced during runtime

Name	Size
CC-HITLT Plot Sources Expired	2.05 MB
Clock Control Reports Expired	1.45 MB
_build-linkConfigurationTest Expired	12.2 MB
_build-safeDffSynchronizer Expired	2.59 KB
_build-swCcTopologyTest Expired	279 MB
_build-swCcTopologyTest-debug Expired	60.1 MB
_build-transceiversUpTest Expired	12.9 MB
_build-vexRiscvTcpTest Expired	48.2 MB
_build-vexRiscvTcpTest-debug Expired	23.5 KB
_build-vexRiscvTest Expired	40.2 MB
_build-vexRiscvTest-debug Expired	176 KB