Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference

In this repository we present Logic Shrinkage, a fine-grained netlist pruning methodology enabling K to be automatically learned for every K-input LUT in a neural network targeted for FPGA inference.

Logic Shrinkage is developed from LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators. Please checkout our previous repository and publications (conference paper and/or journal article) on LUTNet.

Repo organisation

We separated ImageNet from small-scale networks due to slight differences in training environments. Below is an overview of sub-directories.

• instructions: detailed instructions on reproducing our results from scratch
• lutnet/h5py-2-hls: script which converts pretrained network (.h5) into HLS header files (.h) and LUT array RTLs (.v)
• lutnet/src/library: HLS library
• lutnet/src/network: Vivado synthesis code
• lutnet/src/network/LUTNET_c6 (or LUTNET_MNIST if dataset is MNIST, LUTNET_IMAGENET if ImageNet): HLS project
• lutnet/src/network/vivado_out: Vivado synthesis output project
• training-software: Tensorflow-based training project
• training-software/artefact/2_residuals.h5: Training output

Prerequisites

For training Logic Shrinkage, you should have the following packages installed:

• Keras (v2)
• TensorFlow

We recommend using Nvidia's docker containers for TensorFlow to setup training environments. We developed the project using 21.06-tf1-py3 for MNIST-CIFAR-SVHN, and 21.06-tf2-py3 for ImageNet, respectively.

For hardware synthesis, we developed and tested the project with Vivado (+ HLS) 2016.3. Newer versions of Vivado HLS do not work with our project. In newer versions of Vivado HLS, loop unrolling factors are limited, reducing the area-efficiency advantage of LUTNet.

Results

Dataset	Model	Target layer	Top-1 Accuracy (%)	LUT	FPS (Target layer only)
MNIST	Multilayer Perceptron	All dense layers	97.47	63928	200M
SVHN	CNV	Largest conv layer	96.25	179236	200M
CIFAR-10	CNV	Largest conv layer	84.74	220060	200M
ImageNet	Bi-Real-18	Largest conv layer	53.40	690357	5.56M

Citation

If you make use of this code, please acknowledge us by citing our conference papers (FCCM'19, FPGA'22) and/or journal article:

@inproceedings{lutnet_fccm,
	author={Wang, Erwei and Davis, James J. and Cheung, Peter Y. K. and Constantinides, George A.},
	title={{LUTNet}: Rethinking Inference in {FPGA} Soft Logic},
	booktitle={IEEE International Symposium on Field-Programmable Custom Computing Machines},
	year={2019}
}

@article{lutnet_tc,
	author={Wang, Erwei and Davis, James J. and Cheung, Peter Y. K. and Constantinides, George A.},
	title={{LUTNet}: Learning {FPGA} Configurations for Highly Efficient Neural Network Inference},
	journal={IEEE Transactions on Computers},
	year={2020},
	volume = {69},
	number = {12},
	issn = {1557-9956},
	pages = {1795-1808},
	doi = {10.1109/TC.2020.2978817}
}

@inproceedings{lutnet_ls_fpga,
	author={Wang, Erwei and Davis, James J. and Stavrou, Georgios-Ilias and Cheung, Peter Y. K. and Constantinides, George A. and Abdelfattah, Mohamed},
	title={Logic Shrinkage: Learned {FPGA} Netlist Sparsity for Efficient Neural Network Inference},
	booktitle={ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
	year={2022},
	note={to appear}
}