According to Arm Developer the TPIO lines from the Xilinx SoC must be routed out to the appropriate expansion header (for off-chip parallel trace). Proposed solution for the ZC702 can be found here and the Master answer record here. From there one can find an example design for the ZED board, available here. According to the Arm DSTREAM User Guide from the DS-5 docs using the Mictor cable should be enough for both debugging and tracing.
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Written in tcl
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LOC => Location Constraints
Places a logical element from the netlist to a site on the device
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PACKAGE_PIN
Specifies the location of a design port on a pin of the target device package.
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IOSTANDARD
IOSTANDARD sets an IO Standard to an I/O buffer instance.
Top module not set for fileset 'sources_1'.
Right-click on the BD in the sources window and click "Generate HDL wrapper" - taken from here.
Pin layout is different for ZC702 and ZED Board. According to the ZED board schematics (page 9) D21 and E21 connect to FMC_LA27 which is mapped to the J20 Connector on the MX105, instead of J16. See also the schematics of the ZC702 as reference (page 7). Therefore B15 should be used for PJTAG_TMS and C15 should be used for PJTAG_TCK instead. Additionally it makes sense to use B16 for PJTAG_TDI and B17 for PJTAG_TDO. As additional reference use the FMC XM105 doc and look at the J16 and J20 Connector. To understand the connection of the TRACE_DATA pins on (e.g. TRACE_DATA[0] -> PIN38 -> FMC_LA10_P), take a look at the Mictor 38 pinouts documentation.
The PJTAG is routed to the J16 connector on the XM105 and must be connected to the J19 connector (which loops through to the Mictor connector):
- TCK: J16-6 -> J19-4
- TMS: J16-8 -> J19-9
- TDI: J16-10 -> J19-7
- TDO: J16-12 -> J19-6
Use pause instead of stop tracing, otherwise unknown address/instructions errors are observable.
The I/O Peripherals (IOP) unit contains the data communication peripherals and communicates to external devices through a shared pool of up to 54 dedicated multiuse I/O (MIO) pins. These MIO pins are software-configurable to connect to any of the internal I/O peripherals and static memory controllers. If additional I/O pins beyond the 54 are required, it is possible to route these through the PL to the I/O associated with the PL. This feature is referred to as extendable multiplexed I/O (EMIO).
Extendable multiplexed I/O (EMIO) allows unmapped PS peripherals to access PL I/O.