feat: add basic loongarch64 support

.gitignore

@@ -6,3 +6,4 @@
 actual.out
 qemu.log
 rusty-tags.vi
+.idea

Makefile

@@ -103,8 +103,13 @@ else ifeq ($(ARCH), aarch64)
   ACCEL ?= n
   PLATFORM_NAME ?= aarch64-qemu-virt
   TARGET := aarch64-unknown-none-softfloat
+else ifeq ($(ARCH), loongarch64)
+  ACCEL ?= n
+  PLATFORM_NAME ?= loongarch64-qemu-virt
+  TARGET := loongarch64-unknown-none
+  BUS := pci
 else
-  $(error "ARCH" must be one of "x86_64", "riscv64", or "aarch64")
+  $(error "ARCH" must be one of "x86_64", "riscv64", "aarch64" or "loongarch64")
 endif
 
 export AX_ARCH=$(ARCH)
@@ -118,6 +123,9 @@ export AX_GW=$(GW)
 
 # Binutils
 CROSS_COMPILE ?= $(ARCH)-linux-musl-
+ifeq ($(ARCH), loongarch64)
+	CROSS_COMPILE := $(ARCH)-unknown-linux-gnu-
+endif
 CC := $(CROSS_COMPILE)gcc
 AR := $(CROSS_COMPILE)ar
 RANLIB := $(CROSS_COMPILE)ranlib

apps/exception/expect_debug_loongarch64.out

@@ -0,0 +1,19 @@
+smp = 1
+build_mode = release
+log_level = debug
+
+Primary CPU 0 started,
+Found physcial memory regions:
+ .text (READ | EXECUTE | RESERVED)
+ .rodata (READ | RESERVED)
+ .data .tdata .tbss .percpu (READ | WRITE | RESERVED)
+ .percpu (READ | WRITE | RESERVED)
+ boot stack (READ | WRITE | RESERVED)
+ .bss (READ | WRITE | RESERVED)
+ free memory (READ | WRITE | FREE)
+Initialize platform devices...
+Primary CPU 0 init OK.
+Running exception tests...
+Exception(Breakpoint) @ 0x[0-9a-f]\{16\}
+Exception tests run OK!
+Shutting down...

apps/exception/src/main.rs

@@ -15,6 +15,8 @@ fn raise_break_exception() {
         asm!("brk #0");
         #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
         asm!("ebreak");
+        #[cfg(any(target_arch = "loongarch64"))]
+        asm!("break 0");
     }
 }
 

crates/kernel_guard/src/arch/loongarch64.rs

@@ -0,0 +1,19 @@
+use core::arch::asm;
+
+#[inline]
+pub fn local_irq_save_and_disable() -> usize {
+    let mut flags: usize = 0;
+    let ie_mask: usize = 1 << 2;
+    // clear the `IE` bit, and return the old CSR
+    // unsafe { asm!("csrrd {}, 0x0", out(reg) flags) };
+    unsafe { asm!("csrxchg {}, {}, 0x0", inout(reg)flags, in(reg) ie_mask) };
+    flags & ie_mask
+}
+
+#[inline]
+#[allow(unused_assignments)]
+pub fn local_irq_restore(mut flags: usize) {
+    // restore the `IE` bit
+    let mask: usize = 1 << 2;
+    unsafe { asm!("csrxchg {}, {}, 0x0", inout(reg)flags, in(reg) mask) };
+}

crates/kernel_guard/src/arch/mod.rs

@@ -10,5 +10,8 @@ cfg_if::cfg_if! {
     } else if #[cfg(target_arch = "aarch64")] {
         mod aarch64;
         pub use self::aarch64::*;
+    }else if #[cfg(target_arch = "loongarch64")] {
+        mod loongarch64;
+        pub use self::loongarch64::*;
     }
 }

crates/page_table/src/arch/loongarch64.rs

@@ -0,0 +1,16 @@
+//! LoongArch64 specific page table structures.
+
+use crate::{PageTable64, PagingMetaData};
+
+use page_table_entry::loongarch64::LA64PTE;
+/// Metadata of LoongArch64 page tables.
+#[derive(Copy, Clone, Debug)]
+pub struct LA64MetaData;
+
+impl const PagingMetaData for LA64MetaData {
+    const LEVELS: usize = 4;
+    const PA_MAX_BITS: usize = 48;
+    const VA_MAX_BITS: usize = 48;
+}
+
+pub type LA64PageTable<I> = PageTable64<LA64MetaData, LA64PTE, I>;

crates/page_table/src/arch/mod.rs

@@ -6,3 +6,6 @@ pub mod riscv;
 
 #[cfg(any(target_arch = "aarch64", doc))]
 pub mod aarch64;
+
+#[cfg(any(target_arch = "loongarch64", doc))]
+pub mod loongarch64;

crates/page_table_entry/src/arch/loongarch64.rs

@@ -0,0 +1,148 @@
+//! loongarch64 page table entries.
+
+use crate::{GenericPTE, MappingFlags};
+use core::fmt;
+use memory_addr::PhysAddr;
+
+bitflags::bitflags! {
+    /// Page-table entry flags.
+    #[derive(Debug)]
+    pub struct PTEFlags: usize {
+        /// Whether the PTE is valid.
+        const V = 1 << 0;
+        /// Indicates the virtual page has been written since the last time the
+        /// D bit was cleared.
+        const D = 1 << 1;
+        /// Privilege Level with 2 bits.
+        const PLVL = 1 << 2;
+        const PLVH = 1 << 3;
+        /// Memory Access Type controls the type of access, such as whether it
+        /// can be cached by Cache, etc.
+        const MATL = 1 << 4;
+        const MATH = 1 << 5;
+        /// Designates a global mapping OR Whether the page is huge page.
+        const GH = 1 << 6;
+        /// Whether the physical page is exist.
+        const P = 1 << 7;
+        /// Whether the page is writable.
+        const W = 1 << 8;
+        /// Designates a global mapping when using huge page.
+        const G = 1 << 12;
+        /// Whether the page is not readable.
+        const NR = 1 << 61;
+        /// Whether the page is not executable.
+        const NX = 1 << 62;
+        /// Whether the privilege Level is restricted. When RPLV is 0, the PTE
+        /// can be accessed by any program with privilege Level highter than PLV.
+        const RPLV = 1 << 63;
+    }
+}
+
+impl From<PTEFlags> for MappingFlags {
+    fn from(f: PTEFlags) -> Self {
+        let mut ret = Self::empty();
+        if !f.contains(PTEFlags::NR) {
+            ret |= Self::READ;
+        }
+        if f.contains(PTEFlags::W) {
+            ret |= Self::WRITE;
+        }
+        if !f.contains(PTEFlags::NX) {
+            ret |= Self::EXECUTE;
+        }
+        if f.contains(PTEFlags::PLVL) {
+            if f.contains(PTEFlags::PLVH) {
+                ret |= Self::USER;
+            }
+        }
+        if !f.contains(PTEFlags::MATL) {
+            ret |= Self::DEVICE;
+        }
+
+        ret
+    }
+}
+
+impl From<MappingFlags> for PTEFlags {
+    fn from(f: MappingFlags) -> Self {
+        if f.is_empty() {
+            return Self::empty();
+        }
+        let mut ret = Self::V;
+        if !f.contains(MappingFlags::READ) {
+            ret |= Self::NR;
+        }
+        if f.contains(MappingFlags::WRITE) {
+            ret |= Self::W;
+        }
+        if !f.contains(MappingFlags::EXECUTE) {
+            ret |= Self::NX;
+        }
+        if f.contains(MappingFlags::USER) {
+            ret |= Self::PLVH | Self::PLVL;
+        }
+        if !f.contains(MappingFlags::DEVICE) {
+            ret |= Self::MATL;
+        }
+        ret
+    }
+}
+
+#[derive(Clone, Copy)]
+#[repr(transparent)]
+pub struct LA64PTE(u64);
+
+impl LA64PTE {
+    const PHYS_ADDR_MASK: u64 = 0x0000_ffff_ffff_f000; // bits 12..48
+}
+
+impl GenericPTE for LA64PTE {
+    fn new_page(paddr: PhysAddr, flags: MappingFlags, _is_huge: bool) -> Self {
+        let flags = PTEFlags::from(flags);
+        Self(flags.bits() as u64 | ((paddr.as_usize()) as u64 & Self::PHYS_ADDR_MASK))
+    }
+    fn new_table(paddr: PhysAddr) -> Self {
+        Self(PTEFlags::V.bits() as u64 | ((paddr.as_usize()) as u64 & Self::PHYS_ADDR_MASK))
+    }
+    fn paddr(&self) -> PhysAddr {
+        PhysAddr::from((self.0 & Self::PHYS_ADDR_MASK) as usize)
+    }
+    fn flags(&self) -> MappingFlags {
+        PTEFlags::from_bits_truncate(self.0 as usize).into()
+    }
+
+    fn set_paddr(&mut self, paddr: PhysAddr) {
+        self.0 = (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK)
+    }
+
+    fn set_flags(&mut self, flags: MappingFlags, _is_huge: bool) {
+        let flags = PTEFlags::from(flags);
+        self.0 = (self.0 & Self::PHYS_ADDR_MASK) | flags.bits() as u64;
+    }
+
+    fn is_unused(&self) -> bool {
+        self.0 == 0
+    }
+    fn is_present(&self) -> bool {
+        PTEFlags::from_bits_truncate(self.0 as usize).contains(PTEFlags::V)
+    }
+    fn is_huge(&self) -> bool {
+        false
+    }
+    fn clear(&mut self) {
+        self.0 = 0
+    }
+}
+
+impl fmt::Debug for LA64PTE {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        let mut f = f.debug_struct("LA64PTE");
+        f.field("raw", &self.0)
+            .field("paddr", &self.paddr())
+            .field("flags", &self.flags())
+            .field("is_unused", &self.is_unused())
+            .field("is_present", &self.is_present())
+            .field("is_huge", &self.is_huge())
+            .finish()
+    }
+}

crates/page_table_entry/src/arch/mod.rs

@@ -7,3 +7,6 @@ pub mod riscv;
 // TODO: `#[cfg(any(target_arch = "aarch64", doc))]` does not work.
 #[doc(cfg(target_arch = "aarch64"))]
 pub mod aarch64;
+
+#[doc(cfg(target_arch = "loongarch64"))]
+pub mod loongarch64;

crates/percpu/src/imp.rs

@@ -74,6 +74,8 @@ pub fn get_local_thread_pointer() -> usize {
                 core::arch::asm!("mv {}, gp", out(reg) tp)
             } else if #[cfg(target_arch = "aarch64")] {
                 core::arch::asm!("mrs {}, TPIDR_EL1", out(reg) tp)
+            }else if #[cfg(target_arch = "loongarch64")] {
+                core::arch::asm!("move {}, $tp", out(reg) tp)
             }
         }
     }
@@ -108,6 +110,8 @@ pub fn set_local_thread_pointer(cpu_id: usize) {
                 core::arch::asm!("mv gp, {}", in(reg) tp)
             } else if #[cfg(target_arch = "aarch64")] {
                 core::arch::asm!("msr TPIDR_EL1, {}", in(reg) tp)
+            }else if #[cfg(target_arch = "loongarch64")] {
+                core::arch::asm!("move $r21, {}", in(reg) tp)
             }
         }
     }

crates/percpu_macros/src/arch.rs

@@ -33,6 +33,12 @@ pub fn gen_offset(symbol: &Ident) -> proc_macro2::TokenStream {
                 out(reg) value,
                 VAR = sym #symbol,
             );
+            #[cfg(any(target_arch = "loongarch64"))]
+            ::core::arch::asm!(
+                "la.abs {0}, {VAR}",
+                out(reg) value,
+                VAR = sym #symbol,
+            );
         }
         value
     }
@@ -58,6 +64,8 @@ pub fn gen_current_ptr(symbol: &Ident, ty: &Type) -> proc_macro2::TokenStream {
             ::core::arch::asm!("mrs {}, TPIDR_EL1", out(reg) base);
             #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
             ::core::arch::asm!("mv {}, gp", out(reg) base);
+            #[cfg(any(target_arch = "loongarch64"))]
+            ::core::arch::asm!("move {}, $r21", out(reg) base);
             (base + self.offset()) as *const #ty
         }
     })

modules/axhal/Cargo.toml

@@ -54,5 +54,7 @@ arm_gic = { path = "../../crates/arm_gic" }
 arm_pl011 = { path = "../../crates/arm_pl011" }
 dw_apb_uart = { path = "../../crates/dw_apb_uart" }
 
+[target.'cfg(target_arch = "loongarch64")'.dependencies]
+loongarch64 = {git = "https://github.com/Godones/loongArch64",package = "loongArch64" }
 [build-dependencies]
 axconfig = { path = "../axconfig" }

modules/axhal/linker.lds.S

@@ -64,7 +64,7 @@ SECTIONS
     . = ALIGN(4K);
     _edata = .;
 
-    .bss : ALIGN(4K) {
+    .bss : AT(.) ALIGN(4K) {
         boot_stack = .;
         *(.bss.stack)
         . = ALIGN(4K);