gatemate: start experimenting with ccgm1a1 evb from olimex

gateware/.gitignore

@@ -1,3 +1,4 @@
+build/
 sim/*/*.vcd
 sim/*/__pycache__/
 sim/*/*.xml

gateware/boards/gatematea1_evb/Makefile

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+PROJ = top
+
+PIN_DEF = ./boards/gatematea1_evb/pinmap.ccf
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1
+
+include ./mk/common.mk
+include ./mk/gatemate.mk
+
+ADD_SRC = boards/gatematea1_evb/sysmgr.v \
+		  $(SRC_COMMON)

gateware/boards/gatematea1_evb/pinmap.ccf

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+Pin_in   "CLK"           Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true; # 10MHz CLKIN
+Pin_in   "RESET_BUTTON"  Loc = "IO_SB_B7"; # FPGA_BUT1
+Pin_out  "UART_TX"       Loc = "IO_SA_B6"; # RP2040 UART_RX
+
+# This pinout assumes a ribbon cable IS used and the PMOD is
+# connected through an IDC ribbon to the dev board.
+
+Pin_out     "PMOD_SDIN1" Loc = "IO_EA_A4";
+Pin_in     "PMOD_SDOUT1" Loc = "IO_EA_A5";
+Pin_out      "PMOD_LRCK" Loc = "IO_EA_A6";
+Pin_out      "PMOD_BICK" Loc = "IO_EA_A7";
+Pin_inout "PMOD_I2C_SCL" Loc = "IO_EA_B4";
+Pin_inout "PMOD_I2C_SDA" Loc = "IO_EA_B5";
+Pin_out       "PMOD_PDN" Loc = "IO_EA_B6";
+Pin_out      "PMOD_MCLK" Loc = "IO_EA_B7";

gateware/boards/gatematea1_evb/sysmgr.v

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+`default_nettype none
+
+module sysmgr (
+	input  wire clk_in,
+	input  wire rst_in,
+	output wire clk_256fs,
+	output wire clk_fs,
+	output wire rst_out
+);
+
+wire clk_fb;
+wire pll_lock;
+wire pll_reset;
+wire rst_i;
+
+reg [7:0] rst_cnt;
+reg [7:0] clkdiv;
+
+assign pll_reset = rst_in;
+assign rst_i = ~rst_cnt[7];
+assign rst_out = rst_i;
+assign clk_fs = clkdiv[7];
+
+`ifndef VERILATOR_LINT_ONLY
+
+wire clk270, clk180, clk90, usr_ref_out, usr_pll_lock_stdy;
+
+CC_PLL #(
+    .REF_CLK("10.0"),    // reference input in MHz
+    .OUT_CLK("12.0"),    // pll output frequency in MHz
+    .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
+    .LOW_JITTER(1),      // 0: disable, 1: enable low jitter mode
+    .CI_FILTER_CONST(2), // optional CI filter constant
+    .CP_FILTER_CONST(4)  // optional CP filter constant
+) pll_inst (
+    .CLK_REF(clk_in), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0),
+    .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(pll_lock),
+    .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk_256fs), .CLK_REF_OUT(usr_ref_out)
+);
+
+`endif
+
+always @(posedge clk_in)
+    if (rst_in)
+        rst_cnt <= 8'h0;
+    else if (~rst_cnt[7])
+        rst_cnt <= rst_cnt + 1;
+
+always @(posedge clk_256fs)
+    if (rst_i)
+        clkdiv <= 8'h00;
+    else
+        clkdiv <= clkdiv + 1;
+
+endmodule // sysmgr

gateware/mk/gatemate.mk

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+DEFINES = "$(ADD_DEFINES) -DGATEMATE -D$(HW_REV)"
+
+# Location of GateMate toolchain from colognechip.com (requires sign-up).
+GM_TOOLCHAIN = /opt/cc-toolchain-linux
+
+all: $(BUILD)/$(PROJ).cfg.bit
+
+$(BUILD)/%-synth.v: %.sv $(ADD_SRC) $(ADD_DEPS)
+	$(GM_TOOLCHAIN)/bin/yosys/yosys -f "verilog -sv $(DEFINES)" -ql $(BUILD)/$*.log -p 'synth_gatemate -top top -nomx8 -vlog $@' $< $(ADD_SRC)
+
+%.cfg.bit: $(PIN_DEF) %-synth.v
+	$(GM_TOOLCHAIN)/bin/p_r/p_r \
+	-i $(filter-out $<,$^) \
+	-o $@ \
+	-ccf $(PIN_DEF) \
+	-cCP
+
+.SECONDARY:
+.PHONY: all
+.DEFAULT_GOAL := all