boards/gatemate: add experimental support for CCGM1A1 EVB (#56)

* gatemate: start experimenting with ccgm1a1 evb from olimex

* gatemate: add README, comment on broken I2C and UART mirroring

* gatemate: re-add PLL lock check

* gatemate: remap for official EVB - kind of works

* gatemate: rewrite README for official EVB from CologneChip

* gatemate: update readme to point to board-specific oddities

README.md

@@ -58,6 +58,7 @@ The following development boards have been tested with `eurorack-pmod` and are s
 - Colorlight i5 (ECP5 based)
 - Colorlight i9 (ECP5 based)
 - pico-ice from TinyVision (iCE40 based)
+- CCGM1A1 Gatemate EVB from CologneChip - [`gateware/boards/gatemate_evb/README.md`](experimental! see here)
 
 ## PMOD Pinout
 

gateware/.gitignore

@@ -1,3 +1,4 @@
+build/
 sim/*/*.vcd
 sim/*/__pycache__/
 sim/*/*.xml

gateware/boards/gatemate_evb/Makefile

@@ -0,0 +1,10 @@
+PROJ = top
+
+PIN_DEF = ./boards/gatemate_evb/pinmap.ccf
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1
+
+include ./mk/common.mk
+include ./mk/gatemate.mk
+
+ADD_SRC = boards/gatemate_evb/sysmgr.v \
+		  $(SRC_COMMON)

gateware/boards/gatemate_evb/README.md

@@ -0,0 +1,19 @@
+CologneChip CCGM1A1 Evaluation Board V3.2A
+------------------------------------------
+
+Support for this board currently has a few oddities and should be considered EXPERIMENTAL at the moment.
+
+The following should be noted if you want to use `eurorack-pmod` with the CologneChip EVB:
+
+- Make sure to update `GM_TOOLCHAIN` in `mk/gatemate.mk` to point to your CologneChip toolchain. As of the time of writing, a special nightly build is needed to build the bitstream reliably - but I assume this will be part of the official release in a few weeks.
+- There is no spare pins on the built-in FTDI chip to use for UART, so you need to bring-your-own and connect RX to PMOD B pin 1 if you want to use the debug UART features.
+- The PDN line is not pulled to 3V3 strongly enough by the level translators built into the EVB, which will cause the CODEC to stay offline. I worked around this by shorting PDN and 3V3 on the ribbon cable, doing so should have no adverse consequences.
+- Touch scanning does not work - I am not sure why yet but I suspect it is just another artifact of the level translators as with PDN above.
+
+Given the above, the following invocations seem to work (make sure to switch your board to JTAG mode):
+
+
+```bash
+make HW_REV=HW_R33 BOARD=gatemate_evb CORE=mirror
+./openFPGALoader -b gatemate_evb_jtag build/gatemate_evb/top.cfg_00.cfg.bit
+```

gateware/boards/gatemate_evb/pinmap.ccf

@@ -0,0 +1,20 @@
+Pin_in   "CLK"           Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true; # 10MHz CLKIN
+Pin_in   "RESET_BUTTON"  Loc = "IO_EB_B0"; # SW3
+
+# UART on PMODB, pin 1. Unfortunately we can't easily re-use the
+# existing FTDI on the board as it's wired up to JTAG/SPI.
+Pin_out  "UART_TX"       Loc = "IO_NB_A4";
+
+# This pinout assumes a ribbon cable IS used and the PMOD is
+# connected through an IDC ribbon to the dev board.
+
+# eurorack-pmod on PMODA
+
+Pin_out     "PMOD_SDIN1" Loc = "IO_NB_A0";
+Pin_in     "PMOD_SDOUT1" Loc = "IO_NB_A1";
+Pin_out      "PMOD_LRCK" Loc = "IO_NB_A2";
+Pin_out      "PMOD_BICK" Loc = "IO_NB_A3";
+Pin_inout "PMOD_I2C_SCL" Loc = "IO_NB_B0";
+Pin_inout "PMOD_I2C_SDA" Loc = "IO_NB_B1";
+Pin_out       "PMOD_PDN" Loc = "IO_NB_B2";
+Pin_out      "PMOD_MCLK" Loc = "IO_NB_B3";

gateware/boards/gatemate_evb/sysmgr.v

@@ -0,0 +1,55 @@
+`default_nettype none
+
+module sysmgr (
+	input  wire clk_in,
+	input  wire rst_in,
+	output wire clk_256fs,
+	output wire clk_fs,
+	output wire rst_out
+);
+
+wire clk_fb;
+wire pll_lock;
+wire pll_reset;
+wire rst_i;
+
+reg [7:0] rst_cnt;
+reg [7:0] clkdiv;
+
+assign pll_reset = rst_in;
+assign rst_i = ~rst_cnt[7];
+assign rst_out = rst_i;
+assign clk_fs = clkdiv[7];
+
+`ifndef VERILATOR_LINT_ONLY
+
+wire clk270, clk180, clk90, usr_ref_out, usr_pll_lock_stdy;
+
+CC_PLL #(
+    .REF_CLK("10.0"),    // reference input in MHz
+    .OUT_CLK("12.0"),    // pll output frequency in MHz
+    .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
+    .LOW_JITTER(1),      // 0: disable, 1: enable low jitter mode
+    .CI_FILTER_CONST(2), // optional CI filter constant
+    .CP_FILTER_CONST(4)  // optional CP filter constant
+) pll_inst (
+    .CLK_REF(clk_in), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0),
+    .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(pll_lock),
+    .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk_256fs), .CLK_REF_OUT(usr_ref_out)
+);
+
+`endif
+
+always @(posedge clk_in)
+    if (rst_in || ~usr_pll_lock_stdy)
+        rst_cnt <= 8'h0;
+    else if (~rst_cnt[7])
+        rst_cnt <= rst_cnt + 1;
+
+always @(posedge clk_256fs)
+    if (rst_i)
+        clkdiv <= 8'h00;
+    else
+        clkdiv <= clkdiv + 1;
+
+endmodule // sysmgr

gateware/mk/gatemate.mk

@@ -0,0 +1,20 @@
+DEFINES = "$(ADD_DEFINES) -DGATEMATE -D$(HW_REV)"
+
+# Location of GateMate toolchain from colognechip.com (requires sign-up).
+GM_TOOLCHAIN = /opt/cc-toolchain-linux
+
+all: $(BUILD)/$(PROJ).cfg.bit
+
+$(BUILD)/%-synth.v: %.sv $(ADD_SRC) $(ADD_DEPS)
+	$(GM_TOOLCHAIN)/bin/yosys/yosys -f "verilog -sv $(DEFINES)" -ql $(BUILD)/$*.log -p 'synth_gatemate -top top -nomx8 -vlog $@' $< $(ADD_SRC)
+
+%.cfg.bit: $(PIN_DEF) %-synth.v
+	$(GM_TOOLCHAIN)/bin/p_r/p_r \
+	-i $(filter-out $<,$^) \
+	-o $@ \
+	-ccf $(PIN_DEF) \
+	-cCP
+
+.SECONDARY:
+.PHONY: all
+.DEFAULT_GOAL := all