IRQs: hacky experimental DMA IRQs kind of working

apfaudio · Sep 22, 2023 · a3cb04b · a3cb04b
1 parent 40c18fb
commit a3cb04b
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Showing 4 changed files with 46 additions and 5 deletions.
diff --git a/deps/litex b/deps/litex
diff --git a/firmware/litex-fw/src/log.rs b/firmware/litex-fw/src/log.rs
@@ -5,6 +5,7 @@ use heapless::String;
 use litex_pac as pac;
 use litex_hal::prelude::*;
 use litex_hal::uart::UartError;
+use core::arch::asm;
 
 litex_hal::uart! {
     Uart: pac::UART,
@@ -33,8 +34,26 @@ fn exception_handler(_trap_frame: &riscv_rt::TrapFrame) -> ! {
 
 #[export_name = "DefaultHandler"]
 fn default_handler() {
-    _logger_write(b"default_handler\n");
-    loop {}
+    _logger_write(b"irq\n");
+
+    let mut pending: u32 = 0;
+    unsafe {
+    asm!(
+        "csrr {x}, 0xFC0",
+        x = inout(reg) pending,
+        );
+    }
+
+    if (pending & (1u32 << pac::Interrupt::DMA_WRITER0 as u32)) != 0 {
+        let peripherals = unsafe { pac::Peripherals::steal() };
+        let pending_type = peripherals.DMA_WRITER0.ev_pending.read().bits();
+        info!("dmaw0 {:x}", pending_type);
+        unsafe {
+            peripherals.DMA_WRITER0.ev_pending.write(|w| w.bits(pending_type));
+        }
+    } else {
+        info!("unknown irq!!");
+    }
 }
 
 pub fn _logger_write(bytes: &[u8]) {

diff --git a/firmware/litex-fw/src/main.rs b/firmware/litex-fw/src/main.rs
@@ -7,9 +7,11 @@ use litex_hal::prelude::*;
 use litex_hal::uart::UartError;
 use litex_pac as pac;
 use riscv_rt::entry;
+use riscv;
 use core::sync::atomic::fence;
 use core::sync::atomic::compiler_fence;
 use core::sync::atomic::Ordering;
+use core::arch::asm;
 
 mod log;
 use log::*;
@@ -58,13 +60,31 @@ fn main() -> ! {
         peripherals.DMA_WRITER0.length.write(|w| w.bits(BUF_SZ_BYTES as u32));
         peripherals.DMA_WRITER0.loop_.write(|w| w.bits(1u32));
         peripherals.DMA_WRITER0.enable.write(|w| w.bits(1u32));
+
+        peripherals.DMA_WRITER0.ev_enable.write(|w| w.half().bit(true));
+        peripherals.DMA_WRITER0.ev_enable.write(|w| w.done().bit(true));
+
+        asm!(
+            "li {x}, 0xfff",
+            "csrw mie, {x}",
+            x = out(reg) _,
+            );
+
+        asm!(
+            "li {x}, 0x4",
+            "csrw 0xBC0, {x}",
+            x = out(reg) _,
+            );
+
+        riscv::interrupt::enable();
     }
 
     loop {
         log::info!("READ");
         unsafe {
             fence(Ordering::Release);
             compiler_fence(Ordering::Release);
+            log::info!("{:x}", peripherals.DMA_WRITER0.ev_pending.read().bits());
             let buf_read = BUF_IN.clone();
             for i in 0..BUF_SZ_WORDS {
                 log::info!("{:x}@{:x}", i, buf_read[i]);

diff --git a/sim.py b/sim.py
@@ -9,6 +9,7 @@
 from litex.soc.cores.dma import *
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream import ClockDomainCrossing
+from litex.soc.interconnect.csr_eventmanager import *
 
 from eurorack_pmod_migen.core import *
 from eurorack_pmod_migen.blocks import *
@@ -65,12 +66,13 @@ def add_eurorack_pmod(soc):
         eurorack_pmod.cal_out0.eq(cdc_out0.source.payload.data)
     ]
 
-    # DMA master (ADC -> CDC -> SRAM)
+    # DMA master (ADC -> CDC -> Wishbone)
     soc.submodules.dma_writer0 = WishboneDMAWriter(wishbone.Interface(), endianness="big", with_csr=True)
     soc.bus.add_master(master=soc.dma_writer0.bus)
     soc.comb += cdc_in0.source.connect(soc.dma_writer0.sink)
+    soc.irq.add("dma_writer0", use_loc_if_exists=True)
 
-    # DMA master (SRAM -> CDC -> DAC)
+    # DMA master (Wishbone -> CDC -> DAC)
     soc.submodules.dma_reader0 = WishboneDMAReader(wishbone.Interface(), endianness="big", with_csr=True)
     soc.bus.add_master(master=soc.dma_reader0.bus)
     soc.comb += soc.dma_reader0.source.connect(cdc_out0.sink)