Skip to content

Commit

Permalink
hacky clock on manual first row outs
Browse files Browse the repository at this point in the history
  • Loading branch information
vk2seb committed Dec 31, 2023
1 parent 939157c commit 6e704f2
Show file tree
Hide file tree
Showing 4 changed files with 65 additions and 36 deletions.
2 changes: 1 addition & 1 deletion firmware/cmd.sh
Original file line number Diff line number Diff line change
@@ -1 +1 @@
OBJCOPY=riscv-none-elf-objcopy BOARD=colorlight_i5 CC_riscv32imac_unknown_none_elf=riscv-none-elf-gcc AR_riscv32imac_unknown_none_elf=riscv-none-elf-ar RUST_BACKTRACE=1 ./build.sh
OBJCOPY=riscv32-elf-objcopy BOARD=colorlight_i5 CC_riscv32imac_unknown_none_elf=riscv64-elf-gcc AR_riscv32imac_unknown_none_elf=riscv64-elf-ar RUST_BACKTRACE=1 ./build.sh
14 changes: 14 additions & 0 deletions firmware/polyvec-hal/src/gw.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ pub trait EurorackPmod {
fn led_set(&self, index: usize, value: i8);
fn led_auto(&self, index: usize);
fn input(&self, index: usize) -> i16;
fn output(&self, index: usize, value: i16);
}

pub trait WavetableOscillator {
Expand Down Expand Up @@ -117,6 +118,19 @@ macro_rules! eurorack_pmod {
_ => panic!("bad index"),
}) as i16
}

fn output(&self, index: usize, value: i16) {
match index {
0 => self.csr_cal_out0().write(|w| unsafe { w.bits(value as u32) } ),
1 => self.csr_cal_out1().write(|w| unsafe { w.bits(value as u32) } ),
2 => self.csr_cal_out2().write(|w| unsafe { w.bits(value as u32) } ),
3 => self.csr_cal_out3().write(|w| unsafe { w.bits(value as u32) } ),
_ => panic!("bad index")
};
self.csr_out_mode().write(|w| unsafe { w.bits(
self.csr_out_mode().read().bits() | (1 << index)
) } );
}
})+
};
}
Expand Down
14 changes: 9 additions & 5 deletions firmware/polyvec/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,7 @@ struct State {
voice_manager: VoiceManager,
encoder: Encoder,
last_control_type: Option<opt::NoteControl>,
counter: u32,
}

impl State {
Expand All @@ -214,6 +215,7 @@ impl State {
voice_manager: VoiceManager::new(),
encoder,
last_control_type: None,
counter: 0u32,
}
}

Expand Down Expand Up @@ -353,6 +355,12 @@ impl State {
}
}

// Hacky clock divider + master
let pmod0 = &peripherals.EURORACK_PMOD0;
pmod0.output(0, if (self.counter & (1 << 5)) != 0 { 4000 } else { 0 });
pmod0.output(1, if (self.counter & (1 << 6)) == 0 { 4000 } else { 0 });
self.counter += 1;

self.last_control_type = Some(opts.touch.note_control.value);
}
}
Expand Down Expand Up @@ -525,11 +533,7 @@ fn main() -> ! {
irq0_len_us, trace_main.len_us()).ok();

for (n, v) in touch0.iter().enumerate() {
if opts.touch.led_mirror.value == opt::TouchLedMirror::MirrorOn {
pmod0.led_set(n, (v >> 1) as i8);
} else {
pmod0.led_auto(n);
}
pmod0.led_auto(n);
}

for (n, v) in touch1.iter().enumerate() {
Expand Down
71 changes: 41 additions & 30 deletions rtl/eurorack_pmod_wrapper.py
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
)

class EurorackPmod(Module, AutoCSR):
def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared_pads=None, external_reset=None, sim=False):
def __init__(self, platform, pads, w=16, drive_shared_pads=None, external_reset=None, sim=False):
self.w = w
self.cal_mem_file = os.path.join(SOURCES_ROOT, "cal/cal_mem.hex")
self.codec_cfg_file = os.path.join(SOURCES_ROOT, "drivers/ak4619-cfg.hex")
Expand All @@ -30,10 +30,16 @@ def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared
self.cal_in1 = Signal((w, True))
self.cal_in2 = Signal((w, True))
self.cal_in3 = Signal((w, True))
# Routed to MUX
self.cal_out0 = Signal((w, True))
self.cal_out1 = Signal((w, True))
self.cal_out2 = Signal((w, True))
self.cal_out3 = Signal((w, True))
# Routed to CODEC
self.cal_out_int0 = Signal((w, True))
self.cal_out_int1 = Signal((w, True))
self.cal_out_int2 = Signal((w, True))
self.cal_out_int3 = Signal((w, True))

self.eeprom_mfg = Signal(8)
self.eeprom_dev = Signal(8)
Expand Down Expand Up @@ -139,10 +145,10 @@ def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared
o_cal_in1 = self.cal_in1,
o_cal_in2 = self.cal_in2,
o_cal_in3 = self.cal_in3,
i_cal_out0 = self.cal_out0,
i_cal_out1 = self.cal_out1,
i_cal_out2 = self.cal_out2,
i_cal_out3 = self.cal_out3,
i_cal_out0 = self.cal_out_int0,
i_cal_out1 = self.cal_out_int1,
i_cal_out2 = self.cal_out_int2,
i_cal_out3 = self.cal_out_int3,

# Ports (serialized data fetched over I2C)
o_eeprom_mfg = self.eeprom_mfg,
Expand Down Expand Up @@ -208,16 +214,12 @@ def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared
self.csr_cal_in2 = CSRStatus(16)
self.csr_cal_in3 = CSRStatus(16)

if output_csr_read_only:
self.csr_cal_out0 = CSRStatus(16)
self.csr_cal_out1 = CSRStatus(16)
self.csr_cal_out2 = CSRStatus(16)
self.csr_cal_out3 = CSRStatus(16)
else:
self.csr_cal_out0 = CSRStorage(16)
self.csr_cal_out1 = CSRStorage(16)
self.csr_cal_out2 = CSRStorage(16)
self.csr_cal_out3 = CSRStorage(16)
# 1 == manual CSR control, 0 == audio from cal_outX signals.
self.csr_out_mode = CSRStorage(4, reset=0x0)
self.csr_cal_out0 = CSRStorage(16)
self.csr_cal_out1 = CSRStorage(16)
self.csr_cal_out2 = CSRStorage(16)
self.csr_cal_out3 = CSRStorage(16)

self.csr_eeprom_mfg = CSRStatus(8)
self.csr_eeprom_dev = CSRStatus(8)
Expand Down Expand Up @@ -280,19 +282,28 @@ def __init__(self, platform, pads, w=16, output_csr_read_only=True, drive_shared
self.led5.eq(self.csr_led5.storage),
self.led6.eq(self.csr_led6.storage),
self.led7.eq(self.csr_led7.storage),
]

if output_csr_read_only:
self.comb += [
self.csr_cal_out0.status.eq(self.cal_out0),
self.csr_cal_out1.status.eq(self.cal_out1),
self.csr_cal_out2.status.eq(self.cal_out2),
self.csr_cal_out3.status.eq(self.cal_out3),
]
else:
self.comb += [
self.cal_out0.eq(self.csr_cal_out0.storage),
self.cal_out1.eq(self.csr_cal_out1.storage),
self.cal_out2.eq(self.csr_cal_out2.storage),
self.cal_out3.eq(self.csr_cal_out3.storage),
]
If(self.csr_out_mode.storage[0],
self.cal_out_int0.eq(self.csr_cal_out0.storage)
).Else(
self.cal_out_int0.eq(self.cal_out0)
),

If(self.csr_out_mode.storage[1],
self.cal_out_int1.eq(self.csr_cal_out1.storage)
).Else(
self.cal_out_int1.eq(self.cal_out1)
),

If(self.csr_out_mode.storage[2],
self.cal_out_int2.eq(self.csr_cal_out2.storage)
).Else(
self.cal_out_int2.eq(self.cal_out2)
),

If(self.csr_out_mode.storage[3],
self.cal_out_int3.eq(self.csr_cal_out3.storage)
).Else(
self.cal_out_int3.eq(self.cal_out3)
),
]

0 comments on commit 6e704f2

Please sign in to comment.