unify riscv-rt usage, remove -g3 and add -fno-plt -fno-pic to picolib…

…c and soc common.mak
apfaudio · Mar 17, 2024 · 22b67fb · 22b67fb
1 parent 0411b8c
commit 22b67fb
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Showing 5 changed files with 14 additions and 72 deletions.
diff --git a/deps/litex b/deps/litex
diff --git a/firmware/build.sh b/firmware/build.sh
@@ -30,6 +30,6 @@ cargo build --target=riscv32imac-unknown-none-elf --release
 # Copy it into a binary that litex_term can upload.
 ${OBJCOPY} target/riscv32imac-unknown-none-elf/release/polyvec_main -O binary $BUILD_DIR/rust-fw.bin
 
-cd $FW_ROOT/polyboot
-cargo build --target=riscv32imac-unknown-none-elf -vv --release
-${OBJCOPY} target/riscv32imac-unknown-none-elf/release/polyboot -O binary $BUILD_DIR/bootloader.bin
+#cd $FW_ROOT/polyboot
+#cargo build --target=riscv32imac-unknown-none-elf -vv --release
+#${OBJCOPY} target/riscv32imac-unknown-none-elf/release/polyboot -O binary $BUILD_DIR/bootloader.bin
diff --git a/firmware/deps/generated-litex-pac/Cargo.toml b/firmware/deps/generated-litex-pac/Cargo.toml
@@ -7,8 +7,8 @@ edition = "2021"
 
 [dependencies]
 critical-section = { version = "1.0", optional = true }
-riscv = "0.10.1"
-riscv-rt = { version = "0.11.0", optional = true }
+riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }
+riscv-rt = { path = "../riscv-rt", features = ["single-hart"], optional = true }
 vcell = "0.1.0"
 
 [features]

diff --git a/firmware/polyboot/Cargo.lock b/firmware/polyboot/Cargo.lock
diff --git a/firmware/polyvec/Cargo.lock b/firmware/polyvec/Cargo.lock
+1 −1		litex/soc/software/common.mak
+21 −0		patch_pythondata_software_picolibc.diff