Test leaking memory through cycles

test_regress/t/t_leak_mem.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_leak_mem.v

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+// DESCRIPTION: Verilator: memory management test
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef class Cls;
+
+class Ref;
+   Ref r;
+
+   function void set(Ref obj);
+      r = obj;
+   endfunction
+
+   function Ref get();
+      return r;
+   endfunction
+endclass
+
+module t;
+   Ref cycle;
+
+   initial begin
+      for (integer i = 0; i < 100000; i++) begin
+         cycle = new;
+         cycle.set(cycle);
+      end
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule