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Fix assoc_wildcard and dynarray method tests, isolate invalid width b…
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…ug for dynarrays

Signed-off-by: Krzysztof Boronski <[email protected]>
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kboronski-ant committed Oct 15, 2024
1 parent e14488d commit a39a8a3
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Showing 4 changed files with 83 additions and 5 deletions.
33 changes: 30 additions & 3 deletions test_regress/t/t_assoc_wildcard_method.v
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,20 @@
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);

module t (/*AUTOARG*/);
typedef struct { int x, y; } point;

function automatic int vec_len_squared(point p);
return p.x * p.x + p.y * p.y;
endfunction

initial begin
int q[*];
int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage
point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}};
int qv[$]; // Value returns
int qi[$]; // Index returns
int i;
bit b;
string v;

q = '{"a":1, "b":2, "c":2, "d":4, "e":3};
Expand Down Expand Up @@ -78,7 +86,7 @@ module t (/*AUTOARG*/);
i = qe.sum;
`checkh(i, 32'h0);
i = qe.product;
`checkh(i, 32'h0);
`checkh(i, 32'h1);

q = '{10:32'b1100, 11:32'b1010};
i = q.and;
Expand All @@ -95,11 +103,17 @@ module t (/*AUTOARG*/);
`checkh(i, 32'b0110);

i = qe.and;
`checkh(i, 32'b0);
`checkh(i, 32'hffff_ffff);
i = qe.and with (item + 1);
`checkh(i, 32'hffff_ffff);
i = qe.or;
`checkh(i, 32'b0);
i = qe.or with (item + 1);
`checkh(i, 32'b0);
i = qe.xor;
`checkh(i, 32'b0);
i = qe.xor with (item + 1);
`checkh(i, 32'b0);

i = q.and();
`checkh(i, 32'b1000);
Expand All @@ -115,12 +129,25 @@ module t (/*AUTOARG*/);
`checkh(i, 32'b0110);

i = qe.and();
`checkh(i, 32'b0);
`checkh(i, 32'hffff_ffff);
i = qe.or();
`checkh(i, 32'b0);
i = qe.xor();
`checkh(i, 32'b0);

i = points_q.sum with (vec_len_squared(item));
`checkh(i, 32'h2a);
i = points_q.product with (vec_len_squared(item));
`checkh(i, 32'h6a4);
b = points_q.sum with (vec_len_squared(item) == 5);
`checkh(b, 1'b1);
b = points_q.sum with (vec_len_squared(item) == 0);
`checkh(b, 1'b0);
b = points_q.product with (vec_len_squared(item) inside {5, 17});
`checkh(b, 1'b0);
b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20});
`checkh(b, 1'b1);

$write("*-* All Finished *-*\n");
$finish;
end
Expand Down
4 changes: 2 additions & 2 deletions test_regress/t/t_dynarray_method.v
Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ module t (/*AUTOARG*/);
`checkh(i, 32'h0);

i = de.product;
`checkh(i, 32'h0);
`checkh(i, 32'h1);

d = '{32'b1100, 32'b1010};

Expand All @@ -149,7 +149,7 @@ module t (/*AUTOARG*/);
`checkh(i, 32'b0110);

i = de.and;
`checkh(i, 32'b0);
`checkh(i, 32'hffff_ffff);
i = de.or;
`checkh(i, 32'b0);
i = de.xor;
Expand Down
16 changes: 16 additions & 0 deletions test_regress/t/t_dynarray_method_bad.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('linter')

test.lint(fails=True, expect_filename=test.golden_filename)

test.passes()
35 changes: 35 additions & 0 deletions test_regress/t/t_dynarray_method_bad.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);

module t (/*AUTOARG*/);
string s[] = { "hello", "sad", "sad", "world" };

initial begin
int i;
bit b;

i = s.sum with (item.len);
`checkh(i, 10);
i = s.product with (item.len);
`checkh(i, 24);
b = s.sum with (item == "hello");
`checkh(b, 1'b1);
b = s.sum with (item == "");
`checkh(b, 1'b0);
b = s.product with (item inside {"hello", "sad"});
`checkh(b, 1'b0);
b = s.product with (item inside { "hello", "sad", "world" });
`checkh(b, 1'b1);

$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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