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Signed-off-by: Ryszard Rozak <[email protected]>
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#!/usr/bin/env python3 | ||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
# | ||
# Copyright 2024 by Wilson Snyder. This program is free software; you | ||
# can redistribute it and/or modify it under the terms of either the GNU | ||
# Lesser General Public License Version 3 or the Perl Artistic License | ||
# Version 2.0. | ||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
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import vltest_bootstrap | ||
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test.scenarios('simulator') | ||
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if not test.have_solver: | ||
test.skip("No constraint solver installed") | ||
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test.compile() | ||
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test.execute() | ||
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test.passes() |
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// DESCRIPTION: Verilator: Verilog Test module | ||
// | ||
// This file ONLY is placed under the Creative Commons Public Domain, for | ||
// any use, without warranty, 2024 by Antmicro Ltd. | ||
// SPDX-License-Identifier: CC0-1.0 | ||
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class Foo; | ||
rand int q[$]; | ||
rand int q2[$][$]; | ||
rand int r; | ||
int x = 1; | ||
constraint c { | ||
q.size() == 15; | ||
q2.size() == 10; | ||
} | ||
endclass | ||
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module t; | ||
initial begin | ||
Foo foo = new; | ||
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int res = foo.randomize() with {r < 5;}; | ||
if (res != 1) $stop; | ||
if (foo.q.size() != 15) $stop; | ||
if (foo.q2.size() != 10) $stop; | ||
if (foo.r >= 5) $stop; | ||
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$write("*-* All Finished *-*\n"); | ||
$finish; | ||
end | ||
endmodule |