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caliptra-rtl 26cda9bd [RTL] Remove QSPI/UART and merge AXI module tweaks from FPGA testing (#619)
antmicro · Nov 1, 2024 · ea566dc · ea566dc
1 parent 2be4aa2
commit ea566dc
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/deps.json b/deps.json
@@ -1 +1 @@
-{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "fb49826c16aab4902f2bedb5456f2f9ec118a97a"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "ad30bae95f921c7356abebaf9f1f65230c5c7b9f"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "2bcf063ceb5c06fb4d4af6089a0d437ed4c5ee66"}]}
+{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "fb49826c16aab4902f2bedb5456f2f9ec118a97a"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "ad30bae95f921c7356abebaf9f1f65230c5c7b9f"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "26cda9bd019248a0516427facb2602a9274f1d17"}]}