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index #735

Triggered via schedule December 10, 2024 00:14
Status Failure
Total duration 6m 35s
Artifacts 1

index.yml

on: schedule
update-revisions
1m 0s
update-revisions
Matrix: index-cores
setup-default-service
22s
setup-default-service
Matrix: deploy-to-gcp
gcr-cleaner
0s
gcr-cleaner
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3 errors and 6 warnings
deploy-to-gcp (Cores-VeeR-EL2, https://github.com/chipsalliance/Cores-VeeR-EL2, main, 6d828bc5226...
The job was canceled because "caliptra-rtl_https___gith" failed.
update-revisions
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
setup-default-service
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
index-cores (Cores-VeeR-EL2, https://github.com/chipsalliance/Cores-VeeR-EL2, main, 6d828bc5226fc...: home/runner/work/_actions/antmicro/verible-indexing-action/v1.1.1/build.sh#L39
verible-verilog-kythe-extractor: E1210 00:16:30.423308 1920 verilog_kythe_extractor.cc:218] Encountered some issues while indexing files (could result in missing indexing data): E1210 00:16:30.423333 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423335 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423337 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423339 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423341 1920 verilog_kythe_extractor.cc:222] Unable to find 'pic_map_auto.h' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423342 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423344 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423345 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423347 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423348 1920 verilog_kythe_extractor.cc:222] Syntax error. E1210 00:16:30.423350 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423352 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423354 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423356 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423358 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423359 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423362 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_pdef.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423363 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423365 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423366 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423367 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423368 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423370 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423371 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.vh' among the included paths: design/include, tools/riscv-dv, testbench, . E1210 00:16:30.423373 1920 verilog_kythe_extractor.cc:222] Unable to find 'el2_param.v
index-cores (caliptra-rtl, https://github.com/chipsalliance/caliptra-rtl, main, d371fc4ba2e42433c...: home/runner/work/_actions/antmicro/verible-indexing-action/v1.1.1/build.sh#L39
verible-verilog-kythe-extractor: E1210 00:15:50.428084 1899 verilog_kythe_extractor.cc:218] Encountered some issues while indexing files (could result in missing indexing data): E1210 00:15:50.428608 1899 verilog_kythe_extractor.cc:222] Unable to find 'uvm_macros.svh' among the included paths: src/soc_ifc/rtl, src/soc_ifc/tb, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/sha_accel, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/soc_ifc, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/cptra, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src, src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src, src/libs/rtl, src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies, src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf, src/libs/uvmf/qvip_apb5_slave_dir/config_policies, src/libs/uvmf/qvip_apb5_slave_dir/uvmf, src/caliptra_prim/rtl, src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/tests/src, src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/sequences/src, src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/environment_packages/ECC_env_pkg/src, src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_out_pkg/src, src/ecc/uvmf_ecc/uvmf_template_output/verification_ip/interface_packages/ECC_in_pkg/src, src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/tests/src, src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/sequences/src, src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/environment_packages/SHA512_env_pkg/src, src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_in_pkg/src, src/sha512/uvmf_sha512/uvmf_template_output/verification_ip/interface_packages/SHA512_out_pkg/src, src/riscv_core/veer_el2/rtl, src/riscv_core/veer_el2/rtl/include, src/riscv_core/veer_el2/tb, src/integration/rtl, src/integration/tb, src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src, src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src, src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/c
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