Change project name to topwrap

Internal-tag: [#55720]
Signed-off-by: Robert Winkler <[email protected]>

.github/workflows/pipeline.yml

@@ -76,7 +76,7 @@ jobs:
         with:
           python-version: "3.11"
 
-      - name: Install tuttest and fpga-topwrap
+      - name: Install tuttest and topwrap
         run: |
           python3 -m pip install git+https://github.com/antmicro/tuttest
           tuttest README.md | bash -

MANIFEST.in

@@ -1,5 +1,5 @@
-include fpga_topwrap/interfaces/*
-include fpga_topwrap/ips/*/*
-include fpga_topwrap/templates/core.yaml.j2
-include fpga_topwrap/templates/ipcore_desc.j2.yml
+include topwrap/interfaces/*
+include topwrap/ips/*/*
+include topwrap/templates/core.yaml.j2
+include topwrap/templates/ipcore_desc.j2.yml
 include tests/data/*

README.md

@@ -1,4 +1,4 @@
-# FPGA Topwrap
+# Topwrap
 
 Copyright (c) 2021-2024 [Antmicro](https://antmicro.com)
 
@@ -21,4 +21,4 @@ $(command -v sudo) apt-get install -y git g++ make python3 python3-pip antlr4 li
 pip3 install .
 ```
 
-For more information about Topwrap, see the [Documentation](https://antmicro.github.io/fpga-topwrap/).
+For more information about Topwrap, see the [Documentation](https://antmicro.github.io/topwrap/).

docs/source/cli.md

@@ -5,21 +5,21 @@
 To run Topwrap, use:
 
 ```
-python -m fpga_topwrap build --design project.yml
+python -m topwrap build --design project.yml
 ```
 
 Where `project.yml` should be your file with description of the top module.
 
 You can specify a directory to be scanned for additional sources:
 
 ```
-python -m fpga_topwrap build --sources src --design project.yml
+python -m topwrap build --sources src --design project.yml
 ```
 
 To implement the design for a specific FPGA chip, provide the part name:
 
 ```
-python -m fpga_topwrap build --sources src --design project.yml --part 'xc7z020clg400-3'
+python -m topwrap build --sources src --design project.yml --part 'xc7z020clg400-3'
 ```
 
 (connect-topwrap-to-pm)=
@@ -31,14 +31,14 @@ If you want to use Pipeline Manager as a UI for creating block design, you need
 1. Build and run Pipeline Manager server application.
 
 ```
-python -m fpga_topwrap kpm_build_server
-python -m fpga_topwrap kpm_run_server
+python -m topwrap kpm_build_server
+python -m topwrap kpm_run_server
 ```
 
 2. Run Topwrap's client application, that will connect to a running Pipeline Manager server app.
 
 ```
-python -m fpga_topwrap kpm_client [-h ip_addr] [-p port] FILES
+python -m topwrap kpm_client [-h ip_addr] [-p port] FILES
 ```
 
 Topwrap will then try to connect to the server running on `ip_addr:port` and send a specification generated from `FILES`, which should be IP core description yamls.
@@ -53,7 +53,7 @@ You can also use Topwrap to generate ip core description yamls from HDL sources,
 that can be later used in your `project.yml`:
 
 ```
-python -m fpga_topwrap parse HDL_FILES
+python -m topwrap parse HDL_FILES
 ```
 
 In HDL source files, ports that belong to the same interface (e.g. wishbone or AXI),
@@ -62,13 +62,13 @@ convention is followed in the HDL sources, Topwrap can also divide ports into us
 interfaces, or automatically deduce interfaces names when generating yaml file:
 
 ```
-python -m fpga_topwrap parse --iface wishbone --iface s_axi HDL_FILES
+python -m topwrap parse --iface wishbone --iface s_axi HDL_FILES
 
-python -m fpga_topwrap parse --iface-deduce HDL_FILES
+python -m topwrap parse --iface-deduce HDL_FILES
 ```
 
 To get help, use:
 
 ```
-python -m fpga_topwrap [build|kpm_client|parse] --help
+python -m topwrap [build|kpm_client|parse] --help
 ```

docs/source/conf.py

@@ -34,8 +34,8 @@
 # -- General configuration -----------------------------------------------------
 
 # General information about the project.
-project = u'FPGA Topwrap'
-basic_filename = u'fpga-topwrap'
+project = u'Topwrap'
+basic_filename = u'topwrap'
 authors = u'Antmicro'
 copyright = f'{authors}, {datetime.now().year}'
 
@@ -79,7 +79,7 @@
     html_theme_options,
     html_context
 ) = antmicro_html(
-    gh_slug=environ.get('GITHUB_REPOSITORY', 'antmicro/fpga-towrap'),
+    gh_slug=environ.get('GITHUB_REPOSITORY', 'antmicro/topwrap'),
     pdf_url=f"{basic_filename}.pdf",
 )
 

docs/source/elaboratable_wrapper.md

@@ -5,7 +5,7 @@ Supplied elaboratable must contain a `signature` property and a conforming inter
 Ports' directionality, their names and widths are inferred from it.
 
 ```{eval-rst}
-.. autoclass:: fpga_topwrap.elaboratable_wrapper.ElaboratableWrapper
+.. autoclass:: topwrap.elaboratable_wrapper.ElaboratableWrapper
    :members:
 
    .. automethod:: __init__

docs/source/fusesoc.md

@@ -15,7 +15,7 @@ By default, {class}`FuseSocBuilder` searches for the template file in the direct
 Here's an example of how to generate a simple project:
 
 ```python
-from fpga_topwrap.fuse_helper import FuseSocBuilder
+from topwrap.fuse_helper import FuseSocBuilder
 fuse = FuseSocBuilder()
 
 # add source of the IPs used in the project

docs/source/getting_started.md

@@ -19,7 +19,7 @@
     ```
 
 :::{note}
-To use `fpga_topwrap parse` command you also need to install optional dependencies:
+To use `topwrap parse` command you also need to install optional dependencies:
 ```bash
 pip3 install ".[topwrap-parse]"
 ```
@@ -113,7 +113,7 @@ If you don't create any template a default template bundled with Topwrap will be
 7. Run Topwrap:
 
    ```
-   python -m fpga_topwrap build --design project.yml --sources sources
+   python -m topwrap build --design project.yml --sources sources
    ```
 
 ### Example PWM design

docs/source/helpers.md

@@ -1,27 +1,27 @@
 # Helpers
 
 ```{eval-rst}
-.. autoclass:: fpga_topwrap.interface.InterfaceDef
+.. autoclass:: topwrap.interface.InterfaceDef
    :members:
 
    .. automethod:: __init__
 ```
 
 ```{eval-rst}
-.. autofunction:: fpga_topwrap.interface.get_interface_by_name
+.. autofunction:: topwrap.interface.get_interface_by_name
 ```
 
 ```{eval-rst}
-.. autofunction:: fpga_topwrap.interface.get_interface_by_prefix
+.. autofunction:: topwrap.interface.get_interface_by_prefix
 ```
 
 ```{eval-rst}
-.. autoclass:: fpga_topwrap.config.Config
+.. autoclass:: topwrap.config.Config
    :members:
 
    .. automethod:: __init__
 ```
 
 ```{eval-rst}
-.. autofunction:: fpga_topwrap.util.check_interface_compliance
+.. autofunction:: topwrap.util.check_interface_compliance
 ```

docs/source/ipconnect.md

@@ -19,7 +19,7 @@ Ports and interfaces can be set as external input/output/inout with {code}`make_
 For a wider example of using the {class}`IPConnect` see {ref}`Getting Started <getting-started>`
 
 ```{eval-rst}
-.. autoclass:: fpga_topwrap.ipconnect.IPConnect
+.. autoclass:: topwrap.ipconnect.IPConnect
    :members:
 
    .. automethod:: __init__

docs/source/ipwrapper.md

@@ -4,7 +4,7 @@
 It's used to standardize names of ports that belong to interfaces to ease connecting multiple IPs.
 
 ```{eval-rst}
-.. autoclass:: fpga_topwrap.ipwrapper.IPWrapper
+.. autoclass:: topwrap.ipwrapper.IPWrapper
    :members:
 
    .. automethod:: __init__

docs/source/pipeline_manager.md

@@ -11,11 +11,11 @@ Topwrap can make use of [Kenning Pipeline Manager](https://github.com/antmicro/k
     In order to start creating block design in Pipeline Manager, you need to first build and run a server application - here is a brief instruction on how to achieve this (the process of building and installation of Pipeline Manager is described in detail in its [documentation](https://antmicro.github.io/kenning-pipeline-manager/project-readme.html#building-and-running)):
 
     ```
-    python -m fpga_topwrap kpm_build_server
-    python -m fpga_topwrap kpm_run_server
+    python -m topwrap kpm_build_server
+    python -m topwrap kpm_run_server
     ```
 
-    After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on `127.0.0.1:9000` and you can connect to the web GUI frontend in your browser on `http://127.0.0.1:5000`. 
+    After executing the above-mentioned commands, the Pipeline Manager server is waiting for an external application (i.e. Topwrap) to connect on `127.0.0.1:9000` and you can connect to the web GUI frontend in your browser on `http://127.0.0.1:5000`.
 
 2. Establish connection with Topwrap
 
@@ -26,8 +26,8 @@ Topwrap can make use of [Kenning Pipeline Manager](https://github.com/antmicro/k
 
     An example command, that runs Topwrap's client, may look like this:
     ```
-    python -m fpga_topwrap kpm_client -h 127.0.0.1 -p 9000 \
-        fpga_topwrap/ips/axi/axi_axil_adapter.yaml \
+    python -m topwrap kpm_client -h 127.0.0.1 -p 9000 \
+        topwrap/ips/axi/axi_axil_adapter.yaml \
         examples/pwm/ipcores/{litex_pwm.yml,ps7.yaml}
     ```
 
@@ -91,4 +91,4 @@ If a block design validation returns a warning, it means that the block design c
 
 ### Building design
 
-Once the design has been created and tested for validity, you can build design using `Run` feature. If the design does not contain any errors, this will result in creating a top module, similarly when using Topwrap's `fpga_topwrap build` command.
+Once the design has been created and tested for validity, you can build design using `Run` feature. If the design does not contain any errors, this will result in creating a top module, similarly when using Topwrap's `topwrap build` command.

docs/source/wrapper_port.md

@@ -17,7 +17,7 @@ See {ref}`Port slicing <port-slicing>` to know more about `bounds`.
 This is used in {code}`IPWrapper` class implementation and there should be no need to use {class}`WrapperPort` individually.
 
 ```{eval-rst}
-.. autoclass:: fpga_topwrap.amaranth_helpers.WrapperPort
+.. autoclass:: topwrap.amaranth_helpers.WrapperPort
    :members:
 
    .. automethod:: __init__

examples/hdmi/Makefile

@@ -7,10 +7,10 @@ build:
 	mkdir build
 
 parse:
-	fpga_topwrap parse --iface-deduce sources/clock_crossing.v sources/ps7.v
+	topwrap parse --iface-deduce sources/clock_crossing.v sources/ps7.v
 
 generate: build
-	fpga_topwrap build --design project.yml --sources sources
+	topwrap build --design project.yml --sources sources
 
 copy_sources: build
 	cp -rf sources/ build/
@@ -33,4 +33,3 @@ clean:
 	rm -rf build/*
 
 .PHONY: clean copy_sources fusesoc_init generate copy_sources snickerdoodle zvb
-

examples/hdmi/README.md

@@ -1,4 +1,4 @@
-# FPGA Topwrap HDMI example setup
+# Topwrap HDMI example setup
 
 Copyright (c) 2021-2024 [Antmicro](https://antmicro.com)
 

examples/inout/Makefile

@@ -29,10 +29,10 @@ TARGET  := 	zynq
 all: bit
 
 parse: clean setup
-	fpga_topwrap parse --iface-deduce ${SOURCE_FILES} --dest-dir=${IPCORES_DIR}/
+	topwrap parse --iface-deduce ${SOURCE_FILES} --dest-dir=${IPCORES_DIR}/
 
 generate: parse copy_sources
-	fpga_topwrap build --design ${DESIGN} --part ${PART} --sources ${SOURCE_DIR}
+	topwrap build --design ${DESIGN} --part ${PART} --sources ${SOURCE_DIR}
 
 # -------------------------------------
 # Bitstream generation
@@ -59,4 +59,3 @@ clean:
 	rm -rf ${BUILD_DIR}/* ${IPCORES_DIR}/*
 
 .PHONY: setup clean fusesoc_init generate copy_sources bit parse all
-

examples/inout/README.md

@@ -1,4 +1,4 @@
-# FPGA Topwrap example: inout
+# Topwrap example: inout
 
 Copyright (c) 2023-2024 [Antmicro](https://antmicro.com)
 

examples/pwm/Makefile

@@ -7,10 +7,10 @@ build:
 	mkdir build
 
 parse:
-	fpga_topwrap parse --iface-deduce sources/litex_pwm.v sources/ps7.v
+	topwrap parse --iface-deduce sources/litex_pwm.v sources/ps7.v
 
 generate: build
-	fpga_topwrap build --design project.yml --sources sources --part xc7z010clg400-1
+	topwrap build --design project.yml --sources sources --part xc7z010clg400-1
 
 copy_sources: build
 	cp -rf sources/ build/

examples/pwm/README.md

@@ -1,4 +1,4 @@
-# FPGA Topwrap PWM example setup
+# Topwrap PWM example setup
 
 Copyright (c) 2021-2024 [Antmicro](https://antmicro.com)
 

pyproject.toml

@@ -6,7 +6,7 @@ requires = ["setuptools"]
 build-backend = "setuptools.build_meta"
 
 [project]
-name = "fpga_topwrap"
+name = "topwrap"
 version = "0.0.1"
 requires-python = ">=3.8"
 authors = [{name = "Antmicro"}]
@@ -46,10 +46,10 @@ tests = [
 ]
 
 [project.scripts]
-fpga_topwrap = "fpga_topwrap.cli:main"
+topwrap = "topwrap.cli:main"
 
 [tool.setuptools]
-packages = ["fpga_topwrap"]
+packages = ["topwrap"]
 
 [tool.black]
 line-length = 100

tests/data/data_kpm/specification_hdmi.json

@@ -9,7 +9,7 @@
   },
   "nodes": [
     {
-      "additionalData": "fpga_topwrap/ips/axi/axi_axil_adapter.yaml",
+      "additionalData": "topwrap/ips/axi/axi_axil_adapter.yaml",
       "category": "IPcore",
       "interfaces": [
         {
@@ -78,7 +78,7 @@
       "type": "axi_axil_adapter"
     },
     {
-      "additionalData": "fpga_topwrap/ips/axi/axi_interconnect.yaml",
+      "additionalData": "topwrap/ips/axi/axi_interconnect.yaml",
       "category": "IPcore",
       "interfaces": [
         {
@@ -198,7 +198,7 @@
       "type": "axi_interconnect"
     },
     {
-      "additionalData": "fpga_topwrap/ips/axi/axi_protocol_converter.yaml",
+      "additionalData": "topwrap/ips/axi/axi_protocol_converter.yaml",
       "category": "IPcore",
       "interfaces": [
         {
@@ -236,7 +236,7 @@
       "type": "axi_protocol_converter"
     },
     {
-      "additionalData": "fpga_topwrap/ips/axi/axis_async_fifo.yaml",
+      "additionalData": "topwrap/ips/axi/axis_async_fifo.yaml",
       "category": "IPcore",
       "interfaces": [
         {
@@ -359,7 +359,7 @@
       "type": "axis_async_fifo"
     },
     {
-      "additionalData": "fpga_topwrap/ips/axi/axis_dwidth_converter.yaml",
+      "additionalData": "topwrap/ips/axi/axis_dwidth_converter.yaml",
       "category": "IPcore",
       "interfaces": [
         {

tests/data/data_kpm/specification_pwm.json

@@ -9,7 +9,7 @@
   },
   "nodes": [
     {
-      "additionalData": "fpga_topwrap/ips/axi/axi_axil_adapter.yaml",
+      "additionalData": "topwrap/ips/axi/axi_axil_adapter.yaml",
       "category": "IPcore",
       "interfaces": [
         {

tests/tests_build/test_design.py

@@ -4,6 +4,6 @@
 
 class TestDesign:
     def test_design(self):
-        from fpga_topwrap.design import build_design_from_yaml
+        from topwrap.design import build_design_from_yaml
 
         build_design_from_yaml("tests/data/data_build/design.yaml", "build")