Add verilator commands to yaml

Signed-off-by: Ryszard Rozak <[email protected]>
antmicro · Oct 9, 2024 · 0246ca3 · 0246ca3
1 parent 64ae497
commit 0246ca3
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/yaml/simulator.yaml b/yaml/simulator.yaml
@@ -93,6 +93,14 @@
     cmd: >
       <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim
 
+- tool: verilator
+  compile:
+    cmd:
+      - "verilator --binary -I$RV_ROOT/tools/riscv-dv/ $UVM_DIR/uvm.sv -I$UVM_DIR -f $RISCV_DV_ROOT/files.f --timing -DUVM_NO_DPI -Wno-lint -Wno-style -Wno-CONSTRAINTIGN -Wno-ZERODLY -Wno-SYMRSVDWORD --build-jobs `nproc` --output-groups  50"
+  sim:
+    cmd: >
+      obj_dir/Vuvm
+
 - tool: qrun
   compile:
     cmd: