Merge pull request #32 from antmicro/verilator-yosys-upgrade

Build verilator and yosys from sources

.github/benching/action.yml

@@ -33,7 +33,8 @@ runs:
         sudo apt-get update
         sudo apt-get -y install gnat python3 python3-setuptools python3-pip zlib1g-dev tcl8.6-dev git make
         sudo apt-get -y install clang libreadline-dev gawk libffi-dev graphviz xdot libboost-system-dev libboost-python-dev libboost-filesystem-dev
-        sudo apt-get -y install libevent-dev libjson-c-dev ca-certificates
+        sudo apt-get -y install libevent-dev libjson-c-dev ca-certificates quilt
+        sudo apt-get -y install flex bison ccache g++ autoconf perl libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlibc zlib1g zlib1g-dev
         pip3 install gitpython
         sudo ./sbtinstall.sh
         git config --global url.https://github.com/.insteadof "[email protected]:"

.gitmodules

@@ -19,3 +19,9 @@
 	path = third_party/openc906
 	url = https://github.com/Icenowy/openc906.git
     	branch = fpga-optimization
+[submodule "third_party/yosys"]
+	path = third_party/yosys
+	url = https://github.com/YosysHQ/yosys.git
+[submodule "third_party/verilator"]
+	path = third_party/verilator
+	url = https://github.com/verilator/verilator.git

environment.yml

@@ -5,16 +5,10 @@ channels:
     - litex-hub
     - conda-forge
 dependencies:
-    - main::libevent
-    - main::libboost
-    - main::json-c
-    - litex-hub::yosys=0.20_46_g029c2785e=20220819_174700_py37
-    - litex-hub::verilator=4.210_73_g8681861b=20210818_135210
     - litex-hub::gcc-lm32-elf-newlib=9.2.0=20210513_184432
     - litex-hub::gcc-or1k-elf-newlib=9.2.0=20210513_184432
     - antmicro::gcc-ppc64le-linux-musl=12.1.0=20221019_1514
     - antmicro::gcc-riscv64-elf-newlib=12.1.0=20221011_1407
-    - conda-forge::gcc_impl_linux-64=10.3.0
     - pip
     - pip:
         - -r requirements.txt

install.sh

@@ -1,6 +1,7 @@
 #!/bin/bash
 # build essensials
 set -e
+set -x
 
 BASE_DIR=$PWD
 
@@ -17,16 +18,35 @@ cp litex/litex_setup.py .
 chmod +x litex_setup.py
 ./litex_setup.py --init --install --user --dev --config full
 
+# apply cpu patches
+quilt push -a
+
 cd third_party
 
+# yosys install
+cd yosys
+make config-gcc
+echo -n "PREFIX := $BASE_DIR/env/conda/envs/embench-tester" >> Makefile.conf
+make -j $(nproc)
+make install
+cd ..
+
+#verilator install
+cd verilator
+autoconf
+./configure --prefix=$BASE_DIR/env/conda/envs/embench-tester
+make -j $(nproc)
+make install
+cd ..
+
 # ghdl download and install
 cd ghdl
 ./configure --prefix=$BASE_DIR/env/conda/envs/embench-tester
 make -j $(nproc)
 make install
 cd ..
 
-# yosys-gdhl-plugin download and install
+# ghdl-yosys-plugin download and install
 cd ghdl-yosys-plugin
 make -j $(nproc)
 make install

patches/mor1kx.patch

@@ -0,0 +1,17 @@
+Index: embench-tester/pythondata-cpu-mor1kx/pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu.v
+===================================================================
+--- embench-tester.orig/pythondata-cpu-mor1kx/pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu.v
++++ embench-tester/pythondata-cpu-mor1kx/pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu.v
+@@ -197,11 +197,11 @@ module mor1kx_cpu
+
+ 	// synthesis translate_off
+ `ifndef SYNTHESIS
++`include "mor1kx_utils.vh"
+    /* Provide interface hooks for register functions. */
+    generate
+       if (OPTION_CPU=="CAPPUCCINO") begin : monitor
+
+-`include "mor1kx_utils.vh"
+          localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
+                                                        OPTION_RF_NUM_SHADOW_GPR);
+

patches/series

@@ -0,0 +1 @@
+mor1kx.patch