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Support Intel Meteor Lake #196

Merged
merged 5 commits into from
Apr 14, 2024
Merged

Support Intel Meteor Lake #196

merged 5 commits into from
Apr 14, 2024

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TheTumultuousUnicornOfDarkness
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For Meteor Lake, Intel adopted a new branding: Core (Ultra) 3/5/7/9.

Also, there is a new model numbering system:

This is work in progress in 87c282b.

I found 2 CPUID dumps for Meteor Lake:

But libcpuid is not able to properly detect core types for now:

CPUID is present
CPU Info for type #0:
------------------
  arch       : x86
  purpose    : performance
  vendor_str : `GenuineIntel'
  vendor id  : 0
  brand_str  : `Intel(R) Core(TM) Ultra 5 125H'
  family     : 6 (06h)
  model      : 10 (0Ah)
  stepping   : 4 (04h)
  ext_family : 6 (06h)
  ext_model  : 170 (AAh)
  num_cores  : 1
  num_logical: 2
  tot_logical: 18
  affi_mask  : 0x00000003
  L1 D cache : 48 KB
  L1 I cache : 64 KB
  L2 cache   : 2048 KB
  L3 cache   : 18432 KB
  L4 cache   : -1 KB
  L1D assoc. : 12-way
  L1I assoc. : 16-way
  L2 assoc.  : 16-way
  L3 assoc.  : 12-way
  L4 assoc.  : -1-way
  L1D line sz: 64 bytes
  L1I line sz: 64 bytes
  L2 line sz : 64 bytes
  L3 line sz : 64 bytes
  L4 line sz : -1 bytes
  L1D inst.  : 1
  L1I inst.  : 1
  L2 inst.   : 1
  L3 inst.   : 1
  L4 inst.   : 0
  SSE units  : 128 bits (non-authoritative)
  code name  : `Meteor Lake-H (Core Ultra 5)'
  features   : fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
CPU Info for type #1:
------------------
  arch       : x86
  purpose    : efficiency
  vendor_str : `GenuineIntel'
  vendor id  : 0
  brand_str  : `Intel(R) Core(TM) Ultra 5 125H'
  family     : 6 (06h)
  model      : 10 (0Ah)
  stepping   : 4 (04h)
  ext_family : 6 (06h)
  ext_model  : 170 (AAh)
  num_cores  : 8
  num_logical: 8
  tot_logical: 18
  affi_mask  : 0x000003FC
  L1 D cache : 32 KB
  L1 I cache : 64 KB
  L2 cache   : 2048 KB
  L3 cache   : 18432 KB
  L4 cache   : -1 KB
  L1D assoc. : 8-way
  L1I assoc. : 8-way
  L2 assoc.  : 16-way
  L3 assoc.  : 12-way
  L4 assoc.  : -1-way
  L1D line sz: 64 bytes
  L1I line sz: 64 bytes
  L2 line sz : 64 bytes
  L3 line sz : 64 bytes
  L4 line sz : -1 bytes
  L1D inst.  : 8
  L1I inst.  : 8
  L2 inst.   : 2
  L3 inst.   : 1
  L4 inst.   : 0
  SSE units  : 128 bits (non-authoritative)
  code name  : `Meteor Lake-H (Core Ultra 5)'
  features   : fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
CPU Info for type #2:
------------------
  arch       : x86
  purpose    : performance
  vendor_str : `GenuineIntel'
  vendor id  : 0
  brand_str  : `Intel(R) Core(TM) Ultra 5 125H'
  family     : 6 (06h)
  model      : 10 (0Ah)
  stepping   : 4 (04h)
  ext_family : 6 (06h)
  ext_model  : 170 (AAh)
  num_cores  : 3
  num_logical: 6
  tot_logical: 18
  affi_mask  : 0x0000FC00
  L1 D cache : 48 KB
  L1 I cache : 64 KB
  L2 cache   : 2048 KB
  L3 cache   : 18432 KB
  L4 cache   : -1 KB
  L1D assoc. : 12-way
  L1I assoc. : 16-way
  L2 assoc.  : 16-way
  L3 assoc.  : 12-way
  L4 assoc.  : -1-way
  L1D line sz: 64 bytes
  L1I line sz: 64 bytes
  L2 line sz : 64 bytes
  L3 line sz : 64 bytes
  L4 line sz : -1 bytes
  L1D inst.  : 3
  L1I inst.  : 3
  L2 inst.   : 3
  L3 inst.   : 1
  L4 inst.   : 0
  SSE units  : 128 bits (non-authoritative)
  code name  : `Meteor Lake-H (Core Ultra 5)'
  features   : fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
CPU Info for type #3:
------------------
  arch       : x86
  purpose    : efficiency
  vendor_str : `GenuineIntel'
  vendor id  : 0
  brand_str  : `Intel(R) Core(TM) Ultra 5 125H'
  family     : 6 (06h)
  model      : 10 (0Ah)
  stepping   : 4 (04h)
  ext_family : 6 (06h)
  ext_model  : 170 (AAh)
  num_cores  : 2
  num_logical: 2
  tot_logical: 18
  affi_mask  : 0x00030000
  L1 D cache : 32 KB
  L1 I cache : 64 KB
  L2 cache   : 2048 KB
  L3 cache   : -1 KB
  L4 cache   : -1 KB
  L1D assoc. : 8-way
  L1I assoc. : 8-way
  L2 assoc.  : 16-way
  L3 assoc.  : -1-way
  L4 assoc.  : -1-way
  L1D line sz: 64 bytes
  L1I line sz: 64 bytes
  L2 line sz : 64 bytes
  L3 line sz : -1 bytes
  L4 line sz : -1 bytes
  L1D inst.  : 2
  L1I inst.  : 2
  L2 inst.   : 1
  L3 inst.   : 0
  L4 inst.   : 0
  SSE units  : 128 bits (non-authoritative)
  code name  : `Meteor Lake-H (Core Ultra 5)'
  features   : fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx

The problem is Intel is switching to tiles:

Compute tile contains both P-core (Redwood Cove) and E-cores (Crestmont):

But SoC tile also contains 2 LP-E cores (Low Power Crestmont):

And I did not find a way to differentiate Crestmont cores on Compute tile and SoC tile in Intel® 64 and IA-32 Architectures Software Developer’s Manual yet... It seems there is no L3 cache on SoC Tile while L3 cache is present for Crestmont cores on Compute Tile.

@TheTumultuousUnicornOfDarkness
DB: add initial support for Intel Meteor Lake
87c282b
@TheTumultuousUnicornOfDarkness
Rewrite cpu_identify_all() function to support heterogeneous RAW dumps
7ad0a49 
For Meteor Lake CPUs, performance and efficiency cores are mixed (unlike previous CPU generations), so the approach needs to be revisited.
@TheTumultuousUnicornOfDarkness
Tests: fix Bay Trail results
dae1dd3 
Since 7ad0a49, it shows that core count for Intel® Celeron® Processor J1900 and Intel Atom® Processor Z3740 was wrong.
According to Intel, new values are correct:
- https://www.intel.com/content/www/us/en/products/sku/78867/intel-celeron-processor-j1900-2m-cache-up-to-2-42-ghz/specifications.html?wapkw=J1900 ==> 4c/4t
- https://www.intel.com/content/www/us/en/products/sku/76759/intel-atom-processor-z3740-2m-cache-up-to-1-86-ghz/specifications.html ==> 4c/4t
@TheTumultuousUnicornOfDarkness
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In 7ad0a49, I changed the approach in cpu_identify_all(), now it gives something better:

CPU Info for type #0:
------------------
  arch       : x86
  purpose    : performance
  vendor_str : `GenuineIntel'
  vendor id  : 0
  brand_str  : `Intel(R) Core(TM) Ultra 5 125H'
  family     : 6 (06h)
  model      : 10 (0Ah)
  stepping   : 4 (04h)
  ext_family : 6 (06h)
  ext_model  : 170 (AAh)
  num_cores  : 4
  num_logical: 8
  tot_logical: 18
  affi_mask  : 0x0000FC03
  L1 D cache : 48 KB
  L1 I cache : 64 KB
  L2 cache   : 2048 KB
  L3 cache   : 18432 KB
  L4 cache   : -1 KB
  L1D assoc. : 12-way
  L1I assoc. : 16-way
  L2 assoc.  : 16-way
  L3 assoc.  : 12-way
  L4 assoc.  : -1-way
  L1D line sz: 64 bytes
  L1I line sz: 64 bytes
  L2 line sz : 64 bytes
  L3 line sz : 64 bytes
  L4 line sz : -1 bytes
  L1D inst.  : 4
  L1I inst.  : 4
  L2 inst.   : 4
  L3 inst.   : 1
  L4 inst.   : 0
  SSE units  : 128 bits (non-authoritative)
  code name  : `Meteor Lake-H (Core Ultra 5)'
  features   : fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
CPU Info for type #1:
------------------
  arch       : x86
  purpose    : efficiency
  vendor_str : `GenuineIntel'
  vendor id  : 0
  brand_str  : `Intel(R) Core(TM) Ultra 5 125H'
  family     : 6 (06h)
  model      : 10 (0Ah)
  stepping   : 4 (04h)
  ext_family : 6 (06h)
  ext_model  : 170 (AAh)
  num_cores  : 10
  num_logical: 10
  tot_logical: 18
  affi_mask  : 0x000303FC
  L1 D cache : 32 KB
  L1 I cache : 64 KB
  L2 cache   : 2048 KB
  L3 cache   : 18432 KB
  L4 cache   : -1 KB
  L1D assoc. : 8-way
  L1I assoc. : 8-way
  L2 assoc.  : 16-way
  L3 assoc.  : 12-way
  L4 assoc.  : -1-way
  L1D line sz: 64 bytes
  L1I line sz: 64 bytes
  L2 line sz : 64 bytes
  L3 line sz : 64 bytes
  L4 line sz : -1 bytes
  L1D inst.  : 10
  L1I inst.  : 10
  L2 inst.   : 3
  L3 inst.   : 2
  L4 inst.   : 0
  SSE units  : 128 bits (non-authoritative)
  code name  : `Meteor Lake-H (Core Ultra 5)'
  features   : fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx

E-cores and LP E-cores are still displayed both as "efficiency". I found this thread on Intel's forum, maybe Intel will provide information about how to detect LP E-cores.

@TheTumultuousUnicornOfDarkness
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And I did not find a way to differentiate Crestmont cores on Compute tile and SoC tile in Intel® 64 and IA-32 Architectures Software Developer’s Manual yet... It seems there is no L3 cache on SoC Tile while L3 cache is present for Crestmont cores on Compute Tile.

Confirmed by Intel: https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
image

Added detection of LP E-Cores in 5331a4c.

@TheTumultuousUnicornOfDarkness TheTumultuousUnicornOfDarkness marked this pull request as ready for review April 14, 2024 15:18
@TheTumultuousUnicornOfDarkness TheTumultuousUnicornOfDarkness merged commit 13baa0d into master Apr 14, 2024
16 checks passed
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