Pinned Loading

1. processor processor Public

   Verilog

2. chiseltest chiseltest Public

   Forked from ucb-bar/chiseltest

   The batteries-included testing and formal verification library for Chisel-based RTL designs.

   Scala

3. chiselcodegn chiselcodegn Public

   We want to create FIRRTL as a Service. We mix Java and Scala for easily deploy

   Scala