perf(Build): Set Compressed Instruction Set as Default for RISC-V #703
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Description
This PR enables the compressed instruction set extension by default for RISC-V builds.
MARCH
has been changed fromrv32im_zicsr_zifencei
torv32imc_zicsr_zifencei
.This reduces the code size of RISC-V builds.
@rotx-maxim has also reported some performance improvements when using the compressed instruction set, so it seems (at least for now) that there are not significant performance vs code-size tradeoffs.
Uncompressed AI85 PeriphDriver Size
Compressed AI85 PeriphDriver Size
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