axi address width causing overflow

[CharAznable97]

hi, I tried to connect AxiRam with axi interface which has 64 bit addr width...but it resulted into overflow error in C...is this addr size not support in cocotb axi at the moment?

[davekeeshan]

What simulator are you using? I have noticed ghdl has problems with things more than 32 bits

[alexforencich]

This is probably not a cocotbext-axi problem as it works just fine with address widths of 49 bits, which is used in the corundum testbenches for Zynq. It would be nice to see an actual stack trace though, as it could possibly be a cocotb issue, if not a simulator bug.

[CharAznable97]

Hi, I'm using Modelsim simulator running on Linux...the following is the traceback.

200.00ns INFO     cocotb.regression                  run_test_001 failed
                                                    Traceback (most recent call last):
                                                       File "/home/.pyenv/versions/3.10.1/lib/python3.10/site-packages/cocotb/regression.py", line 719, in _my_test
                                                        await function(dut, *args, **kwargs)
                                                       File "/home//test_silex.py", line 91, in run_test
                                                         tb = TB(dut)
                                                       File "/home/test_silex.py", line 51, in __init__
                                                         self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "AxiDma"), dut.refclk, dut.nRst_CPU, size=2**40)
                                                       File "/home/.pyenv/versions/3.10.1/lib/python3.10/site-packages/cocotbext/axi/axi_ram.py", line 50, in __init__
                                                         super().__init__(size, mem, **kwargs)
                                                     File "/home/wangy/.pyenv/versions/3.10.1/lib/python3.10/site-packages/cocotbext/axi/memory.py", line 35, in __init__
                                                        self.mem = mmap.mmap(-1, size)
                                                    OverflowError: Python int too large to convert to C ssize_t

[alexforencich]

Ah, that's a totally different problem than I thought. Currently the way the AxiRam model is implemented, it uses an mmap, which has to fit in the host system. I have a sparse memory model that I have been working on that lazily allocates bytearrays as the memory is accessed, I'll try to get this added to the repo soon.

In the meantime, turn down the size to maybe a few MB. Specifying a smaller size effectively just truncates some high address bits. Depending on what you're doing in the testbench, this may be acceptable.

[CharAznable97]

Thanks, I'll do with the smaller size for now. It should be acceptable. Thanks again for your efforts, I like your cocotb-axi a lot...