Skip to content

Commit

Permalink
Make splitnetlist more efficient, no preliminary opt_clean in submod,…
Browse files Browse the repository at this point in the history
… remove $buf cells in opt_clean
  • Loading branch information
akashlevy committed Jan 11, 2025
1 parent a83e5f4 commit 941d78a
Show file tree
Hide file tree
Showing 3 changed files with 3 additions and 11 deletions.
8 changes: 0 additions & 8 deletions passes/cmds/splitnetlist.cc
Original file line number Diff line number Diff line change
Expand Up @@ -161,10 +161,6 @@ struct SplitNetlist : public ScriptPass {
log("Running splitnetlist pass\n");
log_flush();

// Add buffers for pass-through and connections to constants
// so we can find cells that can be used by submod
Pass::call(design, "bufnorm -buf");

if (debug)
run_pass("write_rtlil post_buf.rtlil");

Expand Down Expand Up @@ -268,10 +264,6 @@ struct SplitNetlist : public ScriptPass {
// Execute the submod command
Pass::call(design, "submod");

// Remove buffers introduced by bufnorm
Pass::call(design, "techmap -D SIMLIB_NOCHECKS -map +/simlib.v t:$buf");
Pass::call(design, "clean");

log("End splitnetlist pass\n");
log_flush();
}
Expand Down
4 changes: 2 additions & 2 deletions passes/hierarchy/submod.cc
Original file line number Diff line number Diff line change
Expand Up @@ -381,8 +381,8 @@ struct SubmodPass : public Pass {

if (opt_name.empty())
{
Pass::call(design, "opt_clean");
log_header(design, "Continuing SUBMOD pass.\n");
// Pass::call(design, "opt_clean");
// log_header(design, "Continuing SUBMOD pass.\n");

std::set<RTLIL::IdString> handled_modules;

Expand Down
2 changes: 1 addition & 1 deletion passes/opt/opt_clean.cc
Original file line number Diff line number Diff line change
Expand Up @@ -601,7 +601,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool unusedbitsattr

std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
Expand Down

0 comments on commit 941d78a

Please sign in to comment.