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Original file line number | Diff line number | Diff line change |
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#include <util/twi.h> | ||
#include <avr/io.h> | ||
#include <stdlib.h> | ||
#include <avr/interrupt.h> | ||
#include <util/twi.h> | ||
#include <stdbool.h> | ||
#include "i2c.h" | ||
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// Limits the amount of we wait for any one i2c transaction. | ||
// Since were running SCL line 100kHz (=> 10μs/bit), and each transactions is | ||
// 9 bits, a single transaction will take around 90μs to complete. | ||
// | ||
// (F_CPU/SCL_CLOCK) => # of μC cycles to transfer a bit | ||
// poll loop takes at least 8 clock cycles to execute | ||
#define I2C_LOOP_TIMEOUT (9+1)*(F_CPU/SCL_CLOCK)/8 | ||
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#define BUFFER_POS_INC() (slave_buffer_pos = (slave_buffer_pos+1)%SLAVE_BUFFER_SIZE) | ||
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volatile uint8_t i2c_slave_buffer[SLAVE_BUFFER_SIZE]; | ||
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static volatile uint8_t slave_buffer_pos; | ||
static volatile bool slave_has_register_set = false; | ||
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// Wait for an i2c operation to finish | ||
inline static | ||
void i2c_delay(void) { | ||
uint16_t lim = 0; | ||
while(!(TWCR & (1<<TWINT)) && lim < I2C_LOOP_TIMEOUT) | ||
lim++; | ||
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// easier way, but will wait slightly longer | ||
// _delay_us(100); | ||
} | ||
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// Setup twi to run at 100kHz | ||
void i2c_master_init(void) { | ||
// no prescaler | ||
TWSR = 0; | ||
// Set TWI clock frequency to SCL_CLOCK. Need TWBR>10. | ||
// Check datasheets for more info. | ||
TWBR = ((F_CPU/SCL_CLOCK)-16)/2; | ||
} | ||
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// Start a transaction with the given i2c slave address. The direction of the | ||
// transfer is set with I2C_READ and I2C_WRITE. | ||
// returns: 0 => success | ||
// 1 => error | ||
uint8_t i2c_master_start(uint8_t address) { | ||
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTA); | ||
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i2c_delay(); | ||
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// check that we started successfully | ||
if ( (TW_STATUS != TW_START) && (TW_STATUS != TW_REP_START)) | ||
return 1; | ||
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TWDR = address; | ||
TWCR = (1<<TWINT) | (1<<TWEN); | ||
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i2c_delay(); | ||
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if ( (TW_STATUS != TW_MT_SLA_ACK) && (TW_STATUS != TW_MR_SLA_ACK) ) | ||
return 1; // slave did not acknowledge | ||
else | ||
return 0; // success | ||
} | ||
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// Finish the i2c transaction. | ||
void i2c_master_stop(void) { | ||
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO); | ||
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uint16_t lim = 0; | ||
while(!(TWCR & (1<<TWSTO)) && lim < I2C_LOOP_TIMEOUT) | ||
lim++; | ||
} | ||
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// Write one byte to the i2c slave. | ||
// returns 0 => slave ACK | ||
// 1 => slave NACK | ||
uint8_t i2c_master_write(uint8_t data) { | ||
TWDR = data; | ||
TWCR = (1<<TWINT) | (1<<TWEN); | ||
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i2c_delay(); | ||
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// check if the slave acknowledged us | ||
return (TW_STATUS == TW_MT_DATA_ACK) ? 0 : 1; | ||
} | ||
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// Read one byte from the i2c slave. If ack=1 the slave is acknowledged, | ||
// if ack=0 the acknowledge bit is not set. | ||
// returns: byte read from i2c device | ||
uint8_t i2c_master_read(int ack) { | ||
TWCR = (1<<TWINT) | (1<<TWEN) | (ack<<TWEA); | ||
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i2c_delay(); | ||
return TWDR; | ||
} | ||
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void i2c_reset_state(void) { | ||
TWCR = 0; | ||
} | ||
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void i2c_slave_init(uint8_t address) { | ||
TWAR = address << 0; // slave i2c address | ||
// TWEN - twi enable | ||
// TWEA - enable address acknowledgement | ||
// TWINT - twi interrupt flag | ||
// TWIE - enable the twi interrupt | ||
TWCR = (1<<TWIE) | (1<<TWEA) | (1<<TWINT) | (1<<TWEN); | ||
} | ||
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ISR(TWI_vect); | ||
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ISR(TWI_vect) { | ||
uint8_t ack = 1; | ||
switch(TW_STATUS) { | ||
case TW_SR_SLA_ACK: | ||
// this device has been addressed as a slave receiver | ||
slave_has_register_set = false; | ||
break; | ||
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case TW_SR_DATA_ACK: | ||
// this device has received data as a slave receiver | ||
// The first byte that we receive in this transaction sets the location | ||
// of the read/write location of the slaves memory that it exposes over | ||
// i2c. After that, bytes will be written at slave_buffer_pos, incrementing | ||
// slave_buffer_pos after each write. | ||
if(!slave_has_register_set) { | ||
slave_buffer_pos = TWDR; | ||
// don't acknowledge the master if this memory loctaion is out of bounds | ||
if ( slave_buffer_pos >= SLAVE_BUFFER_SIZE ) { | ||
ack = 0; | ||
slave_buffer_pos = 0; | ||
} | ||
slave_has_register_set = true; | ||
} else { | ||
i2c_slave_buffer[slave_buffer_pos] = TWDR; | ||
BUFFER_POS_INC(); | ||
} | ||
break; | ||
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case TW_ST_SLA_ACK: | ||
case TW_ST_DATA_ACK: | ||
// master has addressed this device as a slave transmitter and is | ||
// requesting data. | ||
TWDR = i2c_slave_buffer[slave_buffer_pos]; | ||
BUFFER_POS_INC(); | ||
break; | ||
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case TW_BUS_ERROR: // something went wrong, reset twi state | ||
TWCR = 0; | ||
default: | ||
break; | ||
} | ||
// Reset everything, so we are ready for the next TWI interrupt | ||
TWCR |= (1<<TWIE) | (1<<TWINT) | (ack<<TWEA) | (1<<TWEN); | ||
} |
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Original file line number | Diff line number | Diff line change |
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#ifndef I2C_H | ||
#define I2C_H | ||
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#include <stdint.h> | ||
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#ifndef F_CPU | ||
#define F_CPU 16000000UL | ||
#endif | ||
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#define I2C_READ 1 | ||
#define I2C_WRITE 0 | ||
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#define I2C_ACK 1 | ||
#define I2C_NACK 0 | ||
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#define SLAVE_BUFFER_SIZE 0x10 | ||
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// i2c SCL clock frequency | ||
#define SCL_CLOCK 100000L | ||
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extern volatile uint8_t i2c_slave_buffer[SLAVE_BUFFER_SIZE]; | ||
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void i2c_master_init(void); | ||
uint8_t i2c_master_start(uint8_t address); | ||
void i2c_master_stop(void); | ||
uint8_t i2c_master_write(uint8_t data); | ||
uint8_t i2c_master_read(int); | ||
void i2c_reset_state(void); | ||
void i2c_slave_init(uint8_t address); | ||
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#endif |
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Original file line number | Diff line number | Diff line change |
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#include "quantum.h" | ||
#include <avr/wdt.h> | ||
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void promicro_bootloader_jmp(bool program); | ||
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#define KEYMAP( \ | ||
k00, k01, k02, k03, k04, k05, k40, k41, k42, k43, k44, k45, \ | ||
k10, k11, k12, k13, k14, k15, k50, k51, k52, k53, k54, k55, \ | ||
k20, k21, k22, k23, k24, k25, k60, k61, k62, k63, k64, k65, \ | ||
k30, k31, k32, k33, k34, k35, k70, k71, k72, k73, k74, k75 \ | ||
) \ | ||
{ \ | ||
{ k00, k01, k02, k03, k04, k05 }, \ | ||
{ k10, k11, k12, k13, k14, k15 }, \ | ||
{ k20, k21, k22, k23, k24, k25 }, \ | ||
{ k30, k31, k32, k33, k34, k35 }, \ | ||
{ k40, k41, k42, k43, k44, k45 }, \ | ||
{ k50, k51, k52, k53, k54, k55 }, \ | ||
{ k60, k61, k62, k63, k64, k65 }, \ | ||
{ k70, k71, k72, k73, k74, k75 } \ | ||
} |
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