Regenerate using svd2rust 0.31.0

crates/bcm2711-lpa/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "bcm2711-lpa"
-version = "0.2.2"
+version = "0.3.0"
 authors = ["Po-Yi Tsai <[email protected]>"]
 edition = "2021"
 rust-version = "1.65.0"

crates/bcm2711-lpa/src/aux_.rs

@@ -2,10 +2,20 @@
 #[repr(C)]
 #[derive(Debug)]
 pub struct RegisterBlock {
+    irq: IRQ,
+    enables: ENABLES,
+}
+impl RegisterBlock {
     #[doc = "0x00 - Interrupt status"]
-    pub irq: IRQ,
+    #[inline(always)]
+    pub const fn irq(&self) -> &IRQ {
+        &self.irq
+    }
     #[doc = "0x04 - Enable sub-peripherals"]
-    pub enables: ENABLES,
+    #[inline(always)]
+    pub const fn enables(&self) -> &ENABLES {
+        &self.enables
+    }
 }
 #[doc = "IRQ (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq`]
 module"]

crates/bcm2711-lpa/src/aux_/enables.rs

@@ -5,15 +5,15 @@ pub type W = crate::W<ENABLES_SPEC>;
 #[doc = "Field `UART_1` reader - UART1 enabled"]
 pub type UART_1_R = crate::BitReader;
 #[doc = "Field `UART_1` writer - UART1 enabled"]
-pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type UART_1_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SPI_1` reader - SPI1 enabled"]
 pub type SPI_1_R = crate::BitReader;
 #[doc = "Field `SPI_1` writer - SPI1 enabled"]
-pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type SPI_1_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SPI_2` reader - SPI2 enabled"]
 pub type SPI_2_R = crate::BitReader;
 #[doc = "Field `SPI_2` writer - SPI2 enabled"]
-pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type SPI_2_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 0 - UART1 enabled"]
     #[inline(always)]
@@ -42,27 +42,27 @@ impl core::fmt::Debug for R {
 }
 impl core::fmt::Debug for crate::generic::Reg<ENABLES_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        self.read().fmt(f)
+        core::fmt::Debug::fmt(&self.read(), f)
     }
 }
 impl W {
     #[doc = "Bit 0 - UART1 enabled"]
     #[inline(always)]
     #[must_use]
-    pub fn uart_1(&mut self) -> UART_1_W<ENABLES_SPEC, 0> {
-        UART_1_W::new(self)
+    pub fn uart_1(&mut self) -> UART_1_W<ENABLES_SPEC> {
+        UART_1_W::new(self, 0)
     }
     #[doc = "Bit 1 - SPI1 enabled"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_1(&mut self) -> SPI_1_W<ENABLES_SPEC, 1> {
-        SPI_1_W::new(self)
+    pub fn spi_1(&mut self) -> SPI_1_W<ENABLES_SPEC> {
+        SPI_1_W::new(self, 1)
     }
     #[doc = "Bit 2 - SPI2 enabled"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_2(&mut self) -> SPI_2_W<ENABLES_SPEC, 2> {
-        SPI_2_W::new(self)
+    pub fn spi_2(&mut self) -> SPI_2_W<ENABLES_SPEC> {
+        SPI_2_W::new(self, 2)
     }
     #[doc = r" Writes raw bits to the register."]
     #[doc = r""]

crates/bcm2711-lpa/src/aux_/irq.rs

@@ -5,15 +5,15 @@ pub type W = crate::W<IRQ_SPEC>;
 #[doc = "Field `UART_1` reader - UART1 interrupt active"]
 pub type UART_1_R = crate::BitReader;
 #[doc = "Field `UART_1` writer - UART1 interrupt active"]
-pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type UART_1_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SPI_1` reader - SPI1 interrupt active"]
 pub type SPI_1_R = crate::BitReader;
 #[doc = "Field `SPI_1` writer - SPI1 interrupt active"]
-pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type SPI_1_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `SPI_2` reader - SPI2 interrupt active"]
 pub type SPI_2_R = crate::BitReader;
 #[doc = "Field `SPI_2` writer - SPI2 interrupt active"]
-pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type SPI_2_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 0 - UART1 interrupt active"]
     #[inline(always)]
@@ -42,27 +42,27 @@ impl core::fmt::Debug for R {
 }
 impl core::fmt::Debug for crate::generic::Reg<IRQ_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        self.read().fmt(f)
+        core::fmt::Debug::fmt(&self.read(), f)
     }
 }
 impl W {
     #[doc = "Bit 0 - UART1 interrupt active"]
     #[inline(always)]
     #[must_use]
-    pub fn uart_1(&mut self) -> UART_1_W<IRQ_SPEC, 0> {
-        UART_1_W::new(self)
+    pub fn uart_1(&mut self) -> UART_1_W<IRQ_SPEC> {
+        UART_1_W::new(self, 0)
     }
     #[doc = "Bit 1 - SPI1 interrupt active"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_1(&mut self) -> SPI_1_W<IRQ_SPEC, 1> {
-        SPI_1_W::new(self)
+    pub fn spi_1(&mut self) -> SPI_1_W<IRQ_SPEC> {
+        SPI_1_W::new(self, 1)
     }
     #[doc = "Bit 2 - SPI2 interrupt active"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_2(&mut self) -> SPI_2_W<IRQ_SPEC, 2> {
-        SPI_2_W::new(self)
+    pub fn spi_2(&mut self) -> SPI_2_W<IRQ_SPEC> {
+        SPI_2_W::new(self, 2)
     }
     #[doc = r" Writes raw bits to the register."]
     #[doc = r""]

crates/bcm2711-lpa/src/bsc0.rs

@@ -2,22 +2,56 @@
 #[repr(C)]
 #[derive(Debug)]
 pub struct RegisterBlock {
+    c: C,
+    s: S,
+    dlen: DLEN,
+    a: A,
+    fifo: FIFO,
+    div: DIV,
+    del: DEL,
+    clkt: CLKT,
+}
+impl RegisterBlock {
     #[doc = "0x00 - Control"]
-    pub c: C,
+    #[inline(always)]
+    pub const fn c(&self) -> &C {
+        &self.c
+    }
     #[doc = "0x04 - Status"]
-    pub s: S,
+    #[inline(always)]
+    pub const fn s(&self) -> &S {
+        &self.s
+    }
     #[doc = "0x08 - Data length"]
-    pub dlen: DLEN,
+    #[inline(always)]
+    pub const fn dlen(&self) -> &DLEN {
+        &self.dlen
+    }
     #[doc = "0x0c - Slave address"]
-    pub a: A,
+    #[inline(always)]
+    pub const fn a(&self) -> &A {
+        &self.a
+    }
     #[doc = "0x10 - Data FIFO"]
-    pub fifo: FIFO,
+    #[inline(always)]
+    pub const fn fifo(&self) -> &FIFO {
+        &self.fifo
+    }
     #[doc = "0x14 - Clock divider"]
-    pub div: DIV,
+    #[inline(always)]
+    pub const fn div(&self) -> &DIV {
+        &self.div
+    }
     #[doc = "0x18 - Data delay (Values must be under CDIV / 2)"]
-    pub del: DEL,
+    #[inline(always)]
+    pub const fn del(&self) -> &DEL {
+        &self.del
+    }
     #[doc = "0x1c - Clock stretch timeout (broken on 283x)"]
-    pub clkt: CLKT,
+    #[inline(always)]
+    pub const fn clkt(&self) -> &CLKT {
+        &self.clkt
+    }
 }
 #[doc = "C (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c`]
 module"]

crates/bcm2711-lpa/src/bsc0/a.rs

@@ -5,7 +5,7 @@ pub type W = crate::W<A_SPEC>;
 #[doc = "Field `ADDR` reader - Slave address"]
 pub type ADDR_R = crate::FieldReader;
 #[doc = "Field `ADDR` writer - Slave address"]
-pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>;
+pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
 impl R {
     #[doc = "Bits 0:6 - Slave address"]
     #[inline(always)]
@@ -22,15 +22,15 @@ impl core::fmt::Debug for R {
 }
 impl core::fmt::Debug for crate::generic::Reg<A_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        self.read().fmt(f)
+        core::fmt::Debug::fmt(&self.read(), f)
     }
 }
 impl W {
     #[doc = "Bits 0:6 - Slave address"]
     #[inline(always)]
     #[must_use]
-    pub fn addr(&mut self) -> ADDR_W<A_SPEC, 0> {
-        ADDR_W::new(self)
+    pub fn addr(&mut self) -> ADDR_W<A_SPEC> {
+        ADDR_W::new(self, 0)
     }
     #[doc = r" Writes raw bits to the register."]
     #[doc = r""]

crates/bcm2711-lpa/src/bsc0/c.rs

@@ -5,31 +5,31 @@ pub type W = crate::W<C_SPEC>;
 #[doc = "Field `READ` reader - Transfer is read"]
 pub type READ_R = crate::BitReader;
 #[doc = "Field `READ` writer - Transfer is read"]
-pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CLEAR` reader - Clear the FIFO"]
 pub type CLEAR_R = crate::FieldReader;
 #[doc = "Field `CLEAR` writer - Clear the FIFO"]
-pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>;
+pub type CLEAR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
 #[doc = "Field `ST` reader - Start transfer"]
 pub type ST_R = crate::BitReader;
 #[doc = "Field `ST` writer - Start transfer"]
-pub type ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type ST_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `INTD` reader - Interrupt on done"]
 pub type INTD_R = crate::BitReader;
 #[doc = "Field `INTD` writer - Interrupt on done"]
-pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type INTD_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `INTT` reader - Interrupt on TX"]
 pub type INTT_R = crate::BitReader;
 #[doc = "Field `INTT` writer - Interrupt on TX"]
-pub type INTT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type INTT_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `INTR` reader - Interrupt on RX"]
 pub type INTR_R = crate::BitReader;
 #[doc = "Field `INTR` writer - Interrupt on RX"]
-pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type INTR_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `I2CEN` reader - I2C Enable"]
 pub type I2CEN_R = crate::BitReader;
 #[doc = "Field `I2CEN` writer - I2C Enable"]
-pub type I2CEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
+pub type I2CEN_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bit 0 - Transfer is read"]
     #[inline(always)]
@@ -82,51 +82,51 @@ impl core::fmt::Debug for R {
 }
 impl core::fmt::Debug for crate::generic::Reg<C_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        self.read().fmt(f)
+        core::fmt::Debug::fmt(&self.read(), f)
     }
 }
 impl W {
     #[doc = "Bit 0 - Transfer is read"]
     #[inline(always)]
     #[must_use]
-    pub fn read(&mut self) -> READ_W<C_SPEC, 0> {
-        READ_W::new(self)
+    pub fn read(&mut self) -> READ_W<C_SPEC> {
+        READ_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Clear the FIFO"]
     #[inline(always)]
     #[must_use]
-    pub fn clear(&mut self) -> CLEAR_W<C_SPEC, 4> {
-        CLEAR_W::new(self)
+    pub fn clear(&mut self) -> CLEAR_W<C_SPEC> {
+        CLEAR_W::new(self, 4)
     }
     #[doc = "Bit 7 - Start transfer"]
     #[inline(always)]
     #[must_use]
-    pub fn st(&mut self) -> ST_W<C_SPEC, 7> {
-        ST_W::new(self)
+    pub fn st(&mut self) -> ST_W<C_SPEC> {
+        ST_W::new(self, 7)
     }
     #[doc = "Bit 8 - Interrupt on done"]
     #[inline(always)]
     #[must_use]
-    pub fn intd(&mut self) -> INTD_W<C_SPEC, 8> {
-        INTD_W::new(self)
+    pub fn intd(&mut self) -> INTD_W<C_SPEC> {
+        INTD_W::new(self, 8)
     }
     #[doc = "Bit 9 - Interrupt on TX"]
     #[inline(always)]
     #[must_use]
-    pub fn intt(&mut self) -> INTT_W<C_SPEC, 9> {
-        INTT_W::new(self)
+    pub fn intt(&mut self) -> INTT_W<C_SPEC> {
+        INTT_W::new(self, 9)
     }
     #[doc = "Bit 10 - Interrupt on RX"]
     #[inline(always)]
     #[must_use]
-    pub fn intr(&mut self) -> INTR_W<C_SPEC, 10> {
-        INTR_W::new(self)
+    pub fn intr(&mut self) -> INTR_W<C_SPEC> {
+        INTR_W::new(self, 10)
     }
     #[doc = "Bit 15 - I2C Enable"]
     #[inline(always)]
     #[must_use]
-    pub fn i2cen(&mut self) -> I2CEN_W<C_SPEC, 15> {
-        I2CEN_W::new(self)
+    pub fn i2cen(&mut self) -> I2CEN_W<C_SPEC> {
+        I2CEN_W::new(self, 15)
     }
     #[doc = r" Writes raw bits to the register."]
     #[doc = r""]

crates/bcm2711-lpa/src/bsc0/clkt.rs

@@ -5,7 +5,7 @@ pub type W = crate::W<CLKT_SPEC>;
 #[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"]
 pub type TOUT_R = crate::FieldReader<u16>;
 #[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"]
-pub type TOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>;
+pub type TOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
 impl R {
     #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"]
     #[inline(always)]
@@ -22,15 +22,15 @@ impl core::fmt::Debug for R {
 }
 impl core::fmt::Debug for crate::generic::Reg<CLKT_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        self.read().fmt(f)
+        core::fmt::Debug::fmt(&self.read(), f)
     }
 }
 impl W {
     #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"]
     #[inline(always)]
     #[must_use]
-    pub fn tout(&mut self) -> TOUT_W<CLKT_SPEC, 0> {
-        TOUT_W::new(self)
+    pub fn tout(&mut self) -> TOUT_W<CLKT_SPEC> {
+        TOUT_W::new(self, 0)
     }
     #[doc = r" Writes raw bits to the register."]
     #[doc = r""]