Phase-Locked-Loop

Design PLL in 130nm It is the Workshop to Become a fullest in PLL using skywater-pdk using Google SkyWater 130nm Technology.The spice simulations were done using the Ngspice Open source EDA. The Layout design using Magic and parasitic extraction. The Workshop Carried Out in the below manner:

Day-1 : Basics of PLL

Table of Contents

1. About PLL and its application

2. Componets of PLL

3. Important terms in PLL

4. Design Flow and Lab setup

5. Specifiation

6. Day 2- Pre and Post simulation

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1.About PLL and its application

A phase-locked loop or phase lock loop (PLL), it is an control system that generates output signal whose phase is mimic to the phase of an input signal.it is an important Basic block for radio Frequency application.

Block Diagram

It has two parts compare frequency and frequency mather, Compare frequency helps to compare the difference between the reference and feedback frequency. Frequency mather helps to adjust to mimic feedback frequency with respect to input frequency.

Application node:

It helps to control speed of a motor

More Application:

1.Used in demodulation of frequency modulation (FM)

2.Used in demodulation of frequency-shift keying (FSK)

3.generate Clock multipliers in microprocessors

2.Componets of PLL

1. Phase Frequency Detector

It helps to compare the reference frequency signal(RefCLK) with Output frequency signal(FBCLK) to find out the differnce in the signal. such that if a signal is leading then it termed as output as up. When the signal is down it says that output signal is lagging.

2.Charge Pumb

the output from phase frequency detector is given as input of charge pump.It converts digital measure of phase/frequeny difference into an analog control signal to control the oscillator.wave form of charge pump is shown

3.Low Pass Filter

It is the omplement of high pass filter.it passes signals with a frequency lower than a selected cutoff frequency and attenuates. WithouT THIS PLL doesm't Lock.

4. Votage Controlled Oscillator

It is an oscillator whose oscillation frequency is controlled by a voltage input.

5. Frequency Divider

It is a Concept of series of odd number of inverters,period = 2*delay(inverter)*inverter-count.

Important Terms In PLL

1. Lock Range

PLL ia able to follow input frequency variation once it locked its destinct range.

2.Capture Range

The frequency range PLL is able to lock when starting from an unlocked condition.

3.Setting Time

The time within when the PLL is able to lock in form an unlocked condition.

4. Design flow and Labsetup

NgSpice Tool

Intial flow start with targeted design in NgSpice.NgSpice directly simulates the circuit(.cir) file given and plots the results according to the specifications mentioned in the circuit file. To execute the circuite file, on the CMD window type : directory_name_where_files_are_present file_name.cir

Magic Tool

After down with NgSpice layout design will take place in magic. Magic is used for designing the layout file, writing the GDS file for fabrication and also to extracrt the parisitics. To execute the file, on the CMD window type : directory magic -T technology_file_name_from_PDK layout_file In this project, we have used sky130A.tech for the 130nm node technology from Google Skywater library.

5. Specification

Corner = TT

Supply voltage = 1.8V

Temperature = Room temperature

Input Fmin= 5MHz , Fmax= 12.5MHz

Multiplier = 8x

Jitter (RMS) < 20ns

Duty cycle = 50%

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Day 2 : PLL simulation (Prelayout and Postlayout)

# Table of Contents

1. PreLayout simulation

2. PostLayout simulation

3. Tabeout

4. Acknowlegement

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1. PreLayout Simulation

It is the simulation before design the layout to verify the designed circuit giving the right output

1.Phase Frequency Detector Simulation using ngspice

2.Charge Pump simulation using ngspice

3.Voltage Controlled Oscillator

4.Frequeny Divider

5.Phase Locked Loop

Post layout and Parasitic Extraction

1.Phase frequency Detector

2.Charge Pump

3.MUX

4.Voltage Controlled Oscillator

5. Frequency Divider

Acknowlegement

1. I would like to thank Mr. Kunal Ghosh, co-founder VSD, for providing me with this wonderful 2-day workshop.

2. I would like to thank Ms. Lakshmi S, for fullest guiding on design of PLL.