Add support for SVF files to write to external flash (using Master SPI mode). #136
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Thanks for your work, I'll need a few days to check this and review it properly but its not forgotten :) In the mean time:
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…I mode). Enabled under --svf mode by passing --svf-spiflash. Base address can be given with --svf-spibase. Signed-off-by: Gary Wong <[email protected]>
The produced XSVF makes use of the Lattice LCOUNT/LDELAY/LSDR extensions. There are two main advantages to XSVF over SVF: 1) potentially smaller output files (when the increased density of binary encoding outweighs the overhead of mandatory TDOs and masks in XSVF); and 2) the LSDR instruction allows polling until the TAP is ready to accept the next command. This is particularly valuable when writing to SPI flash, since the required delay can vary widely depending on the flash device, and without repeated polling we are forced to impose a conservative delay before one check for completion. Signed-off-by: Gary Wong <[email protected]>
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Sorry about the indentation! I've substituted new commits with spaces-only. Yes, everything in this branch is newly written, and I'm happy to contribute it under ISC. |
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Is this branch OK to merge? I'm happy to make any changes required to make reviewing easier. Thanks! |
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Sorry, managed to forget about this. Looks like there are still some indentation issues, otherwise I see no issues. |
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I tested this with a Colorlight 5a-75b 6.1 (which has an ECP5) https://github.com/q3k/chubby75/blob/master/5a-75b/README.md and it didnt work. It didnt gave any errors to me, but the fpga isnt booting to the led blink. I tested with ujprog: ujprog -d -j FLASH -s ../../ghdl-yosys-blink/vhdl_blink-flash.svf ../../ghdl-yosys-blink/vhdl_blink.bitAnd it did work. Am I missing something?
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I don't understand what worked and what didn't ... |
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If I generate the ecppack vhdl_blink_out.config --svf-spiflash --svf vhdl_blink.svf vhdl_blink.bitThe openocd says the write was succesfull, but the code does not work on the fpga (it just boots whatever was in the SPI Flash). But if I generate the svf file with ujprog, it does work and the fpga boots correctly. PS: I didn't used ujprog to program the FPGA, just to generate the SVF file from the bitstream. |
Enabled under --svf mode by passing --svf-spiflash. Base address can be given with --svf-spibase.
Signed-off-by: Gary Wong [email protected]