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EFB configuration bits
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mmicko committed Oct 4, 2023
1 parent e678da4 commit baefddf
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33 changes: 33 additions & 0 deletions fuzzers/machxo2/110-efb-cfg/efb.ncl
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::FROM-WRITER;
design top
{
device
{
architecture xo2c00;
device LCMXO2-1200HC;
package TQFP144;
performance "6";
}
${comment} comp efb
${comment} {
${comment} logical {
${comment} cellmodel-name EFB;
${comment} program "MODE:EFB "
${comment} "EFB:::EFB_SPI=ENABLED,EFB_TC_PORTMODE=WB,EFB_I2C2=ENABLED,EFB_TC=ENABLED, \"
${comment} "EFB_WB_CLK_FREQ=2.1,TC_TOP_SEL=OFF, \"
${comment} "TC_OVERFLOW=DISABLED:${efb}\"
${comment} "WBADRI5=0,WBADRI7=0,UFMSN=1,I2C1SCLI=0, \"
${comment} "I2C1SDAI=0,I2C2SDAI=0, \"
${comment} "TCRSTN=0,TCIC=0,PLL0DATI0=0, \"
${comment} "PLL0DATI1=0,PLL0DATI2=0,PLL0DATI3=0, \"
${comment} "PLL0DATI4=0,PLL0DATI5=0,PLL0DATI6=0, \"
${comment} "PLL0DATI7=0,PLL0ACKI=0,PLL1DATI0=0, \"
${comment} "PLL1DATI1=0,PLL1DATI2=0,PLL1DATI3=0, \"
${comment} "PLL1DATI4=0,PLL1DATI5=0,PLL1DATI6=0, \"
${comment} "PLL1DATI7=0,PLL1ACKI=0 ";
${comment} }
${comment} site EFB;
${comment} }


}
12 changes: 12 additions & 0 deletions fuzzers/machxo2/110-efb-cfg/empty.ncl
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::FROM-WRITER;
design top
{
device
{
architecture xo2c00;
device LCMXO2-1200HC;
package TQFP144;
performance "6";
}

}
79 changes: 79 additions & 0 deletions fuzzers/machxo2/110-efb-cfg/fuzzer.py
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from collections import defaultdict
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import interconnect

job = (FuzzConfig(job="EFB", family="MachXO2", device="LCMXO2-1200HC", ncl="empty.ncl",
tiles=["CIB_R1C5:CIB_CFG1", "CIB_R1C6:CIB_CFG2", "CIB_R1C7:CIB_CFG3"]))

def get_substs(wbrsti="",wbclki="",i2c2scli="", spiscsn="", tcclki=""):
comment =""
efb = ""
if wbrsti == "INV":
efb += "WBRSTI=#INV,"
elif wbrsti == "0":
efb += "WBRSTI=0,"
elif wbrsti == "1":
efb += "WBRSTI=1,"
else:
efb += ""
if wbclki == "INV":
efb += "WBCLKI=#INV,"
elif wbclki == "0":
efb += "WBCLKI=0,"
elif wbclki == "1":
efb += "WBCLKI=1,"
else:
efb += ""
if i2c2scli == "INV":
efb += "I2C2SCLI=#INV,"
elif i2c2scli == "0":
efb += "I2C2SCLI=0,"
elif i2c2scli == "1":
efb += "I2C2SCLI=1,"
else:
efb += ""
if spiscsn == "INV":
efb += "SPISCSN=#INV,"
elif spiscsn == "0":
efb += "SPISCSN=0,"
elif spiscsn == "1":
efb += "SPISCSN=1,"
else:
efb += ""
if tcclki == "INV":
efb += "TCCLKI=#INV,"
elif tcclki == "0":
efb += "TCCLKI=0,"
elif tcclki == "1":
efb += "TCCLKI=1,"
else:
efb += ""
return dict(comment=comment, efb=efb)


def main():
pytrellis.load_database("../../../database")
cfg = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "efb.ncl"

nonrouting.fuzz_enum_setting(cfg, "EFB.WBRSTI", ["WBRSTI", "0", "1", "INV"],
lambda x: get_substs(wbrsti=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.WBCLKI", ["WBCLKI", "0", "1", "INV"],
lambda x: get_substs(wbclki=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.I2C2SCLI", ["I2C2SCLI", "0", "1", "INV"],
lambda x: get_substs(i2c2scli=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.SPISCSN", ["SPISCSN", "0", "1", "INV"],
lambda x: get_substs(spiscsn=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.TCCLKI", ["TCCLKI", "0", "1", "INV"],
lambda x: get_substs(tcclki=x), empty_bitfile, False)

if __name__ == "__main__":
main()
33 changes: 33 additions & 0 deletions fuzzers/machxo3/110-efb-cfg/efb.ncl
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::FROM-WRITER;
design top
{
device
{
architecture xo3c00f;
device LCMXO3LF-1300E;
package WLCSP36;
performance "6";
}
${comment} comp efb
${comment} {
${comment} logical {
${comment} cellmodel-name EFB;
${comment} program "MODE:EFB "
${comment} "EFB:::EFB_SPI=ENABLED,EFB_TC_PORTMODE=WB,EFB_I2C2=ENABLED,EFB_TC=ENABLED, \"
${comment} "EFB_WB_CLK_FREQ=2.1,TC_TOP_SEL=OFF, \"
${comment} "TC_OVERFLOW=DISABLED:${efb}\"
${comment} "WBADRI5=0,WBADRI7=0,UFMSN=1,I2C1SCLI=0, \"
${comment} "I2C1SDAI=0,I2C2SDAI=0, \"
${comment} "TCRSTN=0,TCIC=0,PLL0DATI0=0, \"
${comment} "PLL0DATI1=0,PLL0DATI2=0,PLL0DATI3=0, \"
${comment} "PLL0DATI4=0,PLL0DATI5=0,PLL0DATI6=0, \"
${comment} "PLL0DATI7=0,PLL0ACKI=0,PLL1DATI0=0, \"
${comment} "PLL1DATI1=0,PLL1DATI2=0,PLL1DATI3=0, \"
${comment} "PLL1DATI4=0,PLL1DATI5=0,PLL1DATI6=0, \"
${comment} "PLL1DATI7=0,PLL1ACKI=0 ";
${comment} }
${comment} site EFB;
${comment} }


}
12 changes: 12 additions & 0 deletions fuzzers/machxo3/110-efb-cfg/empty.ncl
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::FROM-WRITER;
design top
{
device
{
architecture xo3c00f;
device LCMXO3LF-1300E;
package WLCSP36;
performance "6";
}

}
79 changes: 79 additions & 0 deletions fuzzers/machxo3/110-efb-cfg/fuzzer.py
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from collections import defaultdict
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import interconnect

job = (FuzzConfig(job="EFB", family="MachXO3", device="LCMXO3LF-1300E", ncl="empty.ncl",
tiles=["CIB_R1C5:CIB_CFG1", "CIB_R1C6:CIB_CFG2", "CIB_R1C7:CIB_CFG3"]))

def get_substs(wbrsti="",wbclki="",i2c2scli="", spiscsn="", tcclki=""):
comment =""
efb = ""
if wbrsti == "INV":
efb += "WBRSTI=#INV,"
elif wbrsti == "0":
efb += "WBRSTI=0,"
elif wbrsti == "1":
efb += "WBRSTI=1,"
else:
efb += ""
if wbclki == "INV":
efb += "WBCLKI=#INV,"
elif wbclki == "0":
efb += "WBCLKI=0,"
elif wbclki == "1":
efb += "WBCLKI=1,"
else:
efb += ""
if i2c2scli == "INV":
efb += "I2C2SCLI=#INV,"
elif i2c2scli == "0":
efb += "I2C2SCLI=0,"
elif i2c2scli == "1":
efb += "I2C2SCLI=1,"
else:
efb += ""
if spiscsn == "INV":
efb += "SPISCSN=#INV,"
elif spiscsn == "0":
efb += "SPISCSN=0,"
elif spiscsn == "1":
efb += "SPISCSN=1,"
else:
efb += ""
if tcclki == "INV":
efb += "TCCLKI=#INV,"
elif tcclki == "0":
efb += "TCCLKI=0,"
elif tcclki == "1":
efb += "TCCLKI=1,"
else:
efb += ""
return dict(comment=comment, efb=efb)


def main():
pytrellis.load_database("../../../database")
cfg = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "efb.ncl"

nonrouting.fuzz_enum_setting(cfg, "EFB.WBRSTI", ["WBRSTI", "0", "1", "INV"],
lambda x: get_substs(wbrsti=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.WBCLKI", ["WBCLKI", "0", "1", "INV"],
lambda x: get_substs(wbclki=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.I2C2SCLI", ["I2C2SCLI", "0", "1", "INV"],
lambda x: get_substs(i2c2scli=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.SPISCSN", ["SPISCSN", "0", "1", "INV"],
lambda x: get_substs(spiscsn=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.TCCLKI", ["TCCLKI", "0", "1", "INV"],
lambda x: get_substs(tcclki=x), empty_bitfile, False)

if __name__ == "__main__":
main()
33 changes: 33 additions & 0 deletions fuzzers/machxo3d/110-efb-cfg/efb.ncl
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::FROM-WRITER;
design top
{
device
{
architecture se5c00;
device LCMXO3D-9400HC;
package CABGA256;
performance "6";
}
${comment} comp efb
${comment} {
${comment} logical {
${comment} cellmodel-name EFB;
${comment} program "MODE:EFBB "
${comment} "EFBB:::EFB_SPI=ENABLED,EFB_TC_PORTMODE=WB,EFB_I2C2=ENABLED,EFB_TC=ENABLED, \"
${comment} "EFB_WB_CLK_FREQ=2.1,TC_TOP_SEL=OFF, \"
${comment} "TC_OVERFLOW=DISABLED:${efb}\"
${comment} "WBADRI5=0,WBADRI7=0,UFMSN=1,I2C1SCLI=0, \"
${comment} "I2C1SDAI=0,I2C2SDAI=0, \"
${comment} "TCRSTN=0,TCIC=0,PLL0DATI0=0, \"
${comment} "PLL0DATI1=0,PLL0DATI2=0,PLL0DATI3=0, \"
${comment} "PLL0DATI4=0,PLL0DATI5=0,PLL0DATI6=0, \"
${comment} "PLL0DATI7=0,PLL0ACKI=0,PLL1DATI0=0, \"
${comment} "PLL1DATI1=0,PLL1DATI2=0,PLL1DATI3=0, \"
${comment} "PLL1DATI4=0,PLL1DATI5=0,PLL1DATI6=0, \"
${comment} "PLL1DATI7=0,PLL1ACKI=0 ";
${comment} }
${comment} site EFB;
${comment} }


}
12 changes: 12 additions & 0 deletions fuzzers/machxo3d/110-efb-cfg/empty.ncl
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::FROM-WRITER;
design top
{
device
{
architecture se5c00;
device LCMXO3D-9400HC;
package CABGA256;
performance "6";
}

}
79 changes: 79 additions & 0 deletions fuzzers/machxo3d/110-efb-cfg/fuzzer.py
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from collections import defaultdict
from fuzzconfig import FuzzConfig
import nonrouting
import pytrellis
import interconnect

job = (FuzzConfig(job="EFB", family="MachXO3D", device="LCMXO3D-9400HC", ncl="empty.ncl",
tiles=["CIB_R1C5:CIB_CFG1", "CIB_R1C6:CIB_CFG2", "CIB_R1C7:CIB_CFG3"]))

def get_substs(wbrsti="",wbclki="",i2c2scli="", spiscsn="", tcclki=""):
comment =""
efb = ""
if wbrsti == "INV":
efb += "WBRSTI=#INV,"
elif wbrsti == "0":
efb += "WBRSTI=0,"
elif wbrsti == "1":
efb += "WBRSTI=1,"
else:
efb += ""
if wbclki == "INV":
efb += "WBCLKI=#INV,"
elif wbclki == "0":
efb += "WBCLKI=0,"
elif wbclki == "1":
efb += "WBCLKI=1,"
else:
efb += ""
if i2c2scli == "INV":
efb += "I2C2SCLI=#INV,"
elif i2c2scli == "0":
efb += "I2C2SCLI=0,"
elif i2c2scli == "1":
efb += "I2C2SCLI=1,"
else:
efb += ""
if spiscsn == "INV":
efb += "SPISCSN=#INV,"
elif spiscsn == "0":
efb += "SPISCSN=0,"
elif spiscsn == "1":
efb += "SPISCSN=1,"
else:
efb += ""
if tcclki == "INV":
efb += "TCCLKI=#INV,"
elif tcclki == "0":
efb += "TCCLKI=0,"
elif tcclki == "1":
efb += "TCCLKI=1,"
else:
efb += ""
return dict(comment=comment, efb=efb)


def main():
pytrellis.load_database("../../../database")
cfg = job
cfg.setup()
empty_bitfile = cfg.build_design(cfg.ncl, {})
cfg.ncl = "efb.ncl"

nonrouting.fuzz_enum_setting(cfg, "EFB.WBRSTI", ["WBRSTI", "0", "1", "INV"],
lambda x: get_substs(wbrsti=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.WBCLKI", ["WBCLKI", "0", "1", "INV"],
lambda x: get_substs(wbclki=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.I2C2SCLI", ["I2C2SCLI", "0", "1", "INV"],
lambda x: get_substs(i2c2scli=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.SPISCSN", ["SPISCSN", "0", "1", "INV"],
lambda x: get_substs(spiscsn=x), empty_bitfile, False)

nonrouting.fuzz_enum_setting(cfg, "EFB.TCCLKI", ["TCCLKI", "0", "1", "INV"],
lambda x: get_substs(tcclki=x), empty_bitfile, False)

if __name__ == "__main__":
main()

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