fix: add (* keep_hierarchy *) attribute to cells

This makes the physical design closer to the source Wokwi design, and prevents yosys from optimizing things like inverter loops (ring oscillators).

src/cells.v

@@ -6,13 +6,15 @@ It's only needed for Wokwi designs.
 
 `define default_netname none
 
+(* keep_hierarchy *)
 module buffer_cell (
     input wire in,
     output wire out
     );
     assign out = in;
 endmodule
 
+(* keep_hierarchy *)
 module and_cell (
     input wire a,
     input wire b,
@@ -22,6 +24,7 @@ module and_cell (
     assign out = a & b;
 endmodule
 
+(* keep_hierarchy *)
 module or_cell (
     input wire a,
     input wire b,
@@ -31,6 +34,7 @@ module or_cell (
     assign out = a | b;
 endmodule
 
+(* keep_hierarchy *)
 module xor_cell (
     input wire a,
     input wire b,
@@ -40,6 +44,7 @@ module xor_cell (
     assign out = a ^ b;
 endmodule
 
+(* keep_hierarchy *)
 module nand_cell (
     input wire a,
     input wire b,
@@ -49,6 +54,7 @@ module nand_cell (
     assign out = !(a&b);
 endmodule
 
+(* keep_hierarchy *)
 module not_cell (
     input wire in,
     output wire out
@@ -57,6 +63,7 @@ module not_cell (
     assign out = !in;
 endmodule
 
+(* keep_hierarchy *)
 module mux_cell (
     input wire a,
     input wire b,
@@ -67,6 +74,7 @@ module mux_cell (
     assign out = sel ? b : a;
 endmodule
 
+(* keep_hierarchy *)
 module dff_cell (
     input wire clk,
     input wire d,
@@ -80,6 +88,7 @@ module dff_cell (
 
 endmodule
 
+(* keep_hierarchy *)
 module dffsr_cell (
     input wire clk,
     input wire d,