Update spike log parsing

Spike output have been updated in latest releases register index is now left align with space padding
ThalesSiliconSecurity · Feb 1, 2023 · a16b627 · a16b627
1 parent 5d1d337
commit a16b627
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/cva6/sim/cva6_spike_log_to_trace_csv.py b/cva6/sim/cva6_spike_log_to_trace_csv.py
@@ -28,7 +28,7 @@
 from lib import *
 
 RD_RE = re.compile(r"(core\s+\d+:\s+)?(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \
-                   "\((?P<bin>.*?)\)(( c\S* 0x[a-f0-9]+)*) (?P<reg>[xf]\s*\d*?) 0x(?P<val>[a-f0-9]+)")
+                   "\((?P<bin>.*?)\)(( c\S* 0x[a-f0-9]+)*) (?P<reg>[xf]\s*\d*?)\s*0x(?P<val>[a-f0-9]+)")
 
 CORE_RE = re.compile(
     r"core\s+\d+:\s+0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$")