Merge pull request openhwgroup#1610 from ASintzoff/cv32a6_v0.1.0/dev

Use cv32a6 v0.1.0/dev as branch for CVA6 verification work instead of cva6/dev one

.github/ISSUE_TEMPLATE/config.yml

@@ -1,4 +1,3 @@
-blank_issues_enabled: false
 contact_links:
   - name: Tasks
     url: https://github.com/openhwgroup/core-v-verif/issues/new?template=task.md

.github/ISSUE_TEMPLATE/projectTask.yaml

@@ -0,0 +1,28 @@
+name: core-v-verif Project Task
+description: Create a core-v-verif Project Task intended for inclusion on an OpenHW project board
+title: "[TASK] title"
+labels: ["task"]
+body:
+- type: checkboxes
+  attributes:
+    label: Is there an existing core-v-verif task for this?
+    description: Please search to see if a task issue already exists for the task you need to create
+    options:
+    - label: I have searched the existing task issues
+      required: true
+- type: textarea
+  attributes:
+    label: Task Description
+    description: A concise description of what needs to be done (user story)
+  validations:
+    required: true
+- type: textarea
+  attributes:
+    label: Description of Done
+    description: What are the criteria for completion of this task?
+  validations:
+    required: true
+- type: markdown
+  attributes:
+    value: |
+      **Keep task progress up to date by adding comments to the task as it progresses.**

.gitignore

@@ -34,7 +34,6 @@ waves.shm/
 *.log
 stdout.txt
 .vscode
-tools/
 cva6/tests/riscv-compliance/
 cva6/tests/riscv-arch-test/
 cva6/tests/riscv-tests/

.readthedocs.yaml

@@ -0,0 +1,19 @@
+# Configuration file for ReadTheDocs, used to render the
+# Verification Strategy to https://docs.openhwgroup.org/projects/core-v-verif.
+# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+version: 2
+
+#build:
+#  os: "ubuntu-20.04"
+#  tools:
+#    python: "3.9"
+
+# Build from the docs/VerifStrat/source directory with Sphinx
+sphinx:
+  configuration: docs/VerifStrat/source/conf.py
+
+# Explicitly set the Python requirements
+python:
+  install:
+    - requirements: docs/VerifStrat/requirements.txt

GitCheats.md

@@ -104,6 +104,11 @@ $ git push -u origin newbranch
 <br>
 The -u switch sets up tracking to the specified remote (in this example, origin).
 
+## Force your forked repo to be the same as upstream
+\# Note: this is a heavy-handed approach.<br>
+$ git fetch upstream<br>
+$ git reset --hard upstream/master<br>
+$ git push origin master --force
 
 ## Using ssh (need to set-up ssh keys first)
 \# git remote set-url origin [email protected]:username/your-repository.git<br>

README.md

@@ -21,6 +21,7 @@
 # core-v-verif
 Functional verification project for the CORE-V family of RISC-V cores.
 
+<!--
 ## NEWS UPDATES:
 **2021-07-15**: The verificaton environment for the [cv32e40s](https://github.com/openhwgroup/cv32e40s) is up and running.
 <br>
@@ -30,11 +31,12 @@ Functional verification project for the CORE-V family of RISC-V cores.
 This tag clones the v1.0.0 release of the CV32E40P CORE-V core and will allow you to reproduce the verification environment as it existed at `RTL Freeze`.
 <br>
 More news is available in the [archive](https://github.com/openhwgroup/core-v-verif/blob/master/NEWS_ARCHIVE.md).
+-->
 
 ## Getting Started
 First, have a look at the [OpenHW Group's website](https://www.openhwgroup.org) to learn a bit more about who we are and what we are doing.
 <br>
-For first time users of CORE-V-VERIF, the **Quick Start Guide** in the [CORE-V-VERIF Verification Strategy](https://core-v-docs-verif-strat.readthedocs.io/en/latest/) is the best place to start.
+For first time users of CORE-V-VERIF, the **Quick Start Guide** in the [CORE-V-VERIF Verification Strategy](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/quick_start.html) is the best place to start.
 
 <!--
 ### Getting started with CV32E4\* cores

bin/README.md

@@ -11,14 +11,20 @@ determine their own directory based on the implementation langugage hooks availa
 For example from a bash-type shell:<br>
 > % export PATH=./core-v-verif/bin:$PATH
 
+Requirements
+============
+Much of the scriptware in CORE-V-VERIF is written in python and makes use of external packages that are not necessarily distributed with python itself.
+An easy way to get the Python plug-ins installed on your machine is:
+> % git clone https://github.com/openhwgroup/core-v-verif.git \<core-v-verif><br>
+> % cd \<core-v-verif>/bin<br>
+> % pip3 install -r requirements.txt<br>
+
 Utility Documentation
-==================================
+=====================
 
 Documentation for each of the utilities are included below.  Each utility should also support a help option
 on the command line for describing options and arguments available.
 
-==================================
-
 ## makeuvmt
 This is a simple wrapper to redirect a make call to any core's UVMT Makefile.  This redirection script
 simply requires that you either:

bin/requirements.txt

@@ -1,7 +1,7 @@
 bitstring==3.1.9
-constraint==0.4.1
+#constraint==0.4.1
 dv==1.0.10
-Jinja2==2.11.3
+Jinja2==3
 junit_xml==1.9
 Pallets_Sphinx_Themes==2.0.2
 pandas==1.3.4

cv32e40s/tb/uvmt/uvmt_cv32e40s.flist

@@ -22,7 +22,7 @@
 -f ${DV_UVML_LOGS_PATH}/uvml_logs_pkg.flist
 -f ${DV_UVML_SB_PATH}/uvml_sb_pkg.flist
 -f ${DV_UVML_MEM_PATH}/uvml_mem_pkg.flist
--f $(DV_SVLIB_PATH)/svlib_pkg.flist
+-f ${DV_SVLIB_PATH}/svlib_pkg.flist
 
 // Agents
 -f ${DV_UVMA_CORE_CNTRL_PATH}/uvma_core_cntrl_pkg.flist

cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck

@@ -73,7 +73,7 @@ g8
 V000
 p33
 sg23
-VVP_IP003_P001_I000
+VVP_FRONTEND_F003_S001_I000
 p34
 sVdescription
 p35
@@ -135,7 +135,7 @@ g8
 V001
 p61
 sg23
-VVP_IP003_P001_I001
+VVP_FRONTEND_F003_S001_I001
 p62
 sg35
 VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict.
@@ -183,7 +183,7 @@ g8
 V002
 p75
 sg23
-VVP_IP003_P001_I002
+VVP_FRONTEND_F003_S001_I002
 p76
 sg35
 VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB.\u000a\u000aElse JALR is not considered as a control flow instruction, which will generate a mispredict.
@@ -260,7 +260,7 @@ g8
 V000
 p101
 sg23
-VVP_IP003_P002_I000
+VVP_FRONTEND_F003_S002_I000
 p102
 sg35
 VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken.
@@ -309,7 +309,7 @@ g8
 V001
 p116
 sg23
-VVP_IP003_P002_I001
+VVP_FRONTEND_F003_S002_I001
 p117
 sg35
 VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken.
@@ -358,7 +358,7 @@ g8
 V002
 p131
 sg23
-VVP_IP003_P002_I002
+VVP_FRONTEND_F003_S002_I002
 p132
 sg35
 VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken.
@@ -434,7 +434,7 @@ g8
 V000
 p156
 sg23
-VVP_IP003_P003_I000
+VVP_FRONTEND_F003_S003_I000
 p157
 sg35
 VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated.
@@ -482,7 +482,7 @@ g8
 V001
 p170
 sg23
-VVP_IP003_P003_I001
+VVP_FRONTEND_F003_S003_I001
 p171
 sg35
 VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated.
@@ -530,7 +530,7 @@ g8
 V002
 p184
 sg23
-VVP_IP003_P003_I002
+VVP_FRONTEND_F003_S003_I002
 p185
 sg35
 VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated.
@@ -606,7 +606,7 @@ g8
 V000
 p209
 sg23
-VVP_IP003_P004_I000
+VVP_FRONTEND_F003_S004_I000
 p210
 sg35
 VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register.
@@ -615,7 +615,7 @@ sg37
 VFRONTEND sub-system/functionality/PC generation stage/Return from env call
 p212
 sg39
-VSet two different addresses for mepc and sepc in CSR registers. Use a arc_test returning from machine env call. Check by assertion that when machine return occurs the mepc address is fetched. Functional cov: execute a machine return.
+VSet two different addresses for mepc and sepc in CSR registers. Use a arc_test returning from machine env call.\u000a\u000a* Check by assertion that when machine return occurs the mepc address is fetched.\u000a* Functional cov: execute a machine return.
 p213
 sg41
 g42
@@ -654,7 +654,7 @@ g8
 V001
 p223
 sg23
-VVP_IP003_P004_I001
+VVP_FRONTEND_F003_S004_I001
 p224
 sg35
 VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register.
@@ -663,7 +663,7 @@ sg37
 VFRONTEND sub-system/functionality/PC generation stage/Return from env call
 p226
 sg39
-VSet two different addresses for mepc and sepc in CSR registers. Use a returning from supervisor env call. Check by assertion that when supervisor return occurs the sepc address is fetched. Functional cov: execute a supervisor return.
+VSet two different addresses for mepc and sepc in CSR registers. Use a returning from supervisor env call.\u000a\u000a* Check by assertion that when supervisor return occurs the sepc address is fetched.\u000a* Functional cov: execute a supervisor return.
 p227
 sg41
 g42
@@ -674,7 +674,7 @@ I0
 sg45
 I1
 sg46
-I16
+I24
 sg47
 g42
 sg48
@@ -730,7 +730,7 @@ g8
 V000
 p248
 sg23
-VVP_IP003_P005_I000
+VVP_FRONTEND_F003_S005_I000
 p249
 sg35
 VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported)
@@ -778,7 +778,7 @@ g8
 V001
 p262
 sg23
-VVP_IP003_P005_I001
+VVP_FRONTEND_F003_S005_I001
 p263
 sg35
 VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported)
@@ -854,7 +854,7 @@ g8
 V000
 p287
 sg23
-VVP_IP003_P006_I000
+VVP_FRONTEND_F003_S006_I000
 p288
 sg35
 VFRONTEND starts fetching from the next instruction again in order to take the up-dated information into account
@@ -930,7 +930,7 @@ g8
 V000
 p312
 sg23
-VVP_IP003_P007_I000
+VVP_FRONTEND_F003_S007_I000
 p313
 sg35
 VThe debug jump is requested by CSR. The address to be jumped into is HW coded.
@@ -1006,7 +1006,7 @@ g8
 V000
 p337
 sg23
-VVP_IP003_P008_I000
+VVP_FRONTEND_F003_S008_I000
 p338
 sg35
 VAll program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline and TLBs
@@ -1082,7 +1082,7 @@ g8
 V000
 p362
 sg23
-VVP_IP003_P009_I000
+VVP_FRONTEND_F003_S009_I000
 p363
 sg35
 VThe next PC can originate from the following sources (listed in order of precedence)
@@ -1130,7 +1130,7 @@ g8
 V002
 p376
 sg23
-VVP_IP003_P009_I002
+VVP_FRONTEND_F003_S009_I002
 p377
 sg35
 VThe next PC can originate from the following sources (listed in order of precedence)
@@ -1180,7 +1180,19 @@ sg85
 (lp392
 sVvptool_gitrev
 p393
-V$Id$
+V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
 p394
-sbtp395
+sVio_fmt_gitrev
+p395
+V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
+p396
+sVconfig_gitrev
+p397
+V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
+p398
+sVymlcfg_gitrev
+p399
+V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
+p400
+sbtp401
 .